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1. 发明申请

US20110198754A1 Semiconductor device including porous layer covered by poreseal layer 有权
标题翻译：半导体器件包括多孔层被孔隙层覆盖
公开(公告)号：US20110198754A1
公开(公告)日：2011-08-18
申请号：US12929699
申请日：2011-02-09
申请人： Masayoshi Tagami , Fuminori Ito
发明人： Masayoshi Tagami , Fuminori Ito
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/3105 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831
摘要： A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.
摘要翻译：一种形成半导体器件的方法包括在多孔绝缘膜上形成沟槽，将包括包含乙烯基的-Si-O-的结构的化学材料放置在多孔绝缘膜的表面上或多孔绝缘膜中，并且执行化学材料的聚合以提供密度高于沟槽表面上的多孔绝缘膜的密度的电介质膜。该结构可以是由式1定义的结构。

2. 发明授权

US08377823B2 Semiconductor device including porous layer covered by poreseal layer 有权
标题翻译：半导体器件包括多孔层被孔隙层覆盖
公开(公告)号：US08377823B2
公开(公告)日：2013-02-19
申请号：US12929699
申请日：2011-02-09
申请人： Masayoshi Tagami , Fuminori Ito
发明人： Masayoshi Tagami , Fuminori Ito
IPC分类号： H01L21/28
CPC分类号： H01L21/3105 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831
摘要： A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.
摘要翻译：一种形成半导体器件的方法包括在多孔绝缘膜上形成沟槽，将包括包含乙烯基的-Si-O-的结构的化学材料放置在多孔绝缘膜的表面上或多孔绝缘膜中，并且执行化学材料的聚合以提供密度高于沟槽表面上的多孔绝缘膜的密度的电介质膜。该结构可以是由式1定义的结构。

3. 发明申请

US20060131754A1 Semiconductor device having trench interconnection and manufacturing method of semiconductor device 有权
标题翻译：具有沟槽互连的半导体器件和半导体器件的制造方法
公开(公告)号：US20060131754A1
公开(公告)日：2006-06-22
申请号：US11317399
申请日：2005-12-23
申请人： Hiroto Ohtake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
发明人： Hiroto Ohtake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
IPC分类号： H01L23/48
CPC分类号： H01L21/76813 , H01L21/31116 , H01L21/31144 , H01L21/3143 , H01L21/31633 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device includes a first interconnection layer and a interlayer insulating layer. The first interconnection layer is formed on a upper side of a substrate, and includes a first interconnection. The interlayer insulating layer is formed on the first interconnection layer, and includes a via connected with the first interconnection at one end of the via and a second interconnection connected with the via at another end of the via. The interlayer insulating layer has a relative dielectric constant lower than that of a silicon oxide film. An upper portion of the interlayer insulating layer includes a silicon-oxide film, a silicon nitride film and a silicon oxide film in order from a lower portion.
摘要翻译：半导体器件包括第一互连层和层间绝缘层。第一互连层形成在基板的上侧，并且包括第一互连。层间绝缘层形成在第一互连层上，并且包括在通孔的一端与第一互连连接的通孔和在通孔的另一端与通孔相连的第二互连。层间绝缘层的相对介电常数比氧化硅膜低。层间绝缘层的上部从下部开始依次包括氧化硅膜，氮化硅膜和氧化硅膜。

4. 发明授权

US07999391B2 Multilayered wiring structure, and method for manufacturing multilayered wiring 有权
标题翻译：多层布线结构以及多层布线的制造方法
公开(公告)号：US07999391B2
公开(公告)日：2011-08-16
申请号：US12278339
申请日：2007-02-06
申请人： Hiroto Ootake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
发明人： Hiroto Ootake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
IPC分类号： H01L29/40
CPC分类号： H01L23/53238 , H01L21/76808 , H01L21/76814 , H01L21/7682 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a wiring of the Damascene structure for preventing the TDDB withstand voltage degradation and for keeping the planarity to prevent the degradation of a focus margin. A trench wiring (213) is formed in an interlayer insulating film, which is composed of a silicon carbide-nitride film (205), a SiOCH film (206) and a silicon oxide film (207) [(e)]. The silicon oxide film (207) is etched at a portion adjacent to the wiring of a polished surface by dry etching or wet etching [(f)]. A silicon carbide-nitride film (SiCN) (214) is formed as a Cu cap film [(g)]. An interlayer insulating film is further formed thereon to form a conductive plug, a trench wiring and so on.
摘要翻译：提供了一种用于防止TDDB耐电压劣化并保持平面性以防止聚焦余量劣化的镶嵌结构的布线。沟槽布线（213）形成在由碳化硅 - 氮化物膜（SiO 2），SiOCH膜（206）和氧化硅膜（207）[（e）]组成的层间绝缘膜中。氧化硅膜（207）通过干蚀刻或湿蚀刻（f）]在与抛光表面的布线相邻的部分被蚀刻。形成碳化硅 - 氮化物膜（SiCN）（214）作为Cu帽膜[（g）]。还在其上形成层间绝缘膜以形成导电插塞，沟槽布线等。

5. 发明授权

US07622808B2 Semiconductor device and having trench interconnection 有权
标题翻译：半导体器件并具有沟槽互连
公开(公告)号：US07622808B2
公开(公告)日：2009-11-24
申请号：US11317399
申请日：2005-12-23
申请人： Hiroto Ohtake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
发明人： Hiroto Ohtake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
IPC分类号： H01L23/48
CPC分类号： H01L21/76813 , H01L21/31116 , H01L21/31144 , H01L21/3143 , H01L21/31633 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device includes a first interconnection layer and a interlayer insulating layer. The first interconnection layer is formed on a upper side of a substrate, and includes a first interconnection. The interlayer insulating layer is formed on the first interconnection layer, and includes a via connected with the first interconnection at one end of the via and a second interconnection connected with the via at another end of the via. The interlayer insulating layer has a relative dielectric constant lower than that of a silicon oxide film. An upper portion of the interlayer insulating layer includes a silicon-oxide film, a silicon nitride film and a silicon oxide film in order from a lower portion.
摘要翻译：半导体器件包括第一互连层和层间绝缘层。第一互连层形成在基板的上侧，并且包括第一互连。层间绝缘层形成在第一互连层上，并且包括在通孔的一端与第一互连连接的通孔和在通孔的另一端与通孔相连的第二互连。层间绝缘层的相对介电常数比氧化硅膜低。层间绝缘层的上部从下部开始依次包括氧化硅膜，氮化硅膜和氧化硅膜。

6. 发明授权

US08198730B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08198730B2
公开(公告)日：2012-06-12
申请号：US12522814
申请日：2008-01-08
申请人： Masayoshi Tagami , Yoshihiro Hayashi , Munehiro Tada , Takahiro Onodera , Naoya Furutake , Makoto Ueki , Mari Amano
发明人： Masayoshi Tagami , Yoshihiro Hayashi , Munehiro Tada , Takahiro Onodera , Naoya Furutake , Makoto Ueki , Mari Amano
IPC分类号： H01L23/52
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/7684 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.
摘要翻译：半导体器件具有包括形成在绝缘膜内的预定区域中的铜互连膜，衬里膜和高熔点金属膜的多层互连。铜互连膜是多晶的，并且占据形成多晶体的晶粒中的单位互连表面的面积的40％以上的晶粒在基板厚度方向上取向为（111）。铜互连膜与贵金属衬垫膜具有晶体一致性。在高熔点金属膜由Ti形成并且贵金属衬垫膜是Ru膜的情况下，Ti的高熔点金属以固态溶解到Ru中以形成贵金属衬垫。因此，铜互连形成为Cu扩散阻挡特性和Cu晶体一致性。

7. 发明授权

US07341937B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07341937B2
公开(公告)日：2008-03-11
申请号：US11174595
申请日：2005-07-06
申请人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
发明人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.
摘要翻译：公开了具有精密加工的双镶嵌结构的半导体器件。半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有沟槽图案。至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

8. 发明授权

US08513114B2 Method for forming a dual damascene interconnect structure 有权
标题翻译：形成双镶嵌互连结构的方法
公开(公告)号：US08513114B2
公开(公告)日：2013-08-20
申请号：US13424954
申请日：2012-03-20
申请人： Masayoshi Tagami
发明人： Masayoshi Tagami
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31116 , H01L21/31144 , H01L21/7682 , H01L2221/1047
摘要： An improved method of forming a semiconductor device including an interconnect layer formed using multilayer hard mask comprising metal mask and dielectric mask is provided. To form the second opening pattern being aligned to the first pattern, after the multilayer hard mask is used at the first step, then the dielectric mask is used to form a damascene structure in an insulator layer at the second step followed by removing the metal mask.
摘要翻译：提供一种改进的形成半导体器件的方法，该半导体器件包括使用包括金属掩模和电介质掩模的多层硬掩模形成的互连层。为了形成与第一图案对准的第二开口图案，在第一步骤使用多层硬掩模之后，使用介电掩模在第二步骤在绝缘体层中形成镶嵌结构，然后除去金属掩模。

9. 发明授权

US06538324B1 Multi-layered wiring layer and method of fabricating the same 有权
标题翻译：多层布线层及其制造方法
公开(公告)号：US06538324B1
公开(公告)日：2003-03-25
申请号：US09596415
申请日：2000-06-19
申请人： Masayoshi Tagami , Yoshihiro Hayashi
发明人： Masayoshi Tagami , Yoshihiro Hayashi
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： There is provided a barrier film preventing diffusion of copper from a copper wiring layer formed on a semiconductor substrate. The barrier film has a multi-layered structure of first and second films wherein the first film is composed of crystalline metal containing nitrogen therein, and the second film is composed of amorphous metal nitride. The barrier film is constituted of common metal atomic species. The barrier film prevents copper diffusion from a copper wiring layer into a semiconductor device, and has sufficient adhesion characteristic to both a copper film and an interlayer insulating film.
摘要翻译：提供了防止铜从形成在半导体衬底上的铜布线层扩散的阻挡膜。阻挡膜具有第一膜和第二膜的多层结构，其中第一膜由其中含有氮的结晶金属构成，第二膜由非晶态金属氮化物构成。阻挡膜由普通金属原子物种构成。阻挡膜防止铜从铜布线层扩散到半导体器件中，并且对铜膜和层间绝缘膜具有足够的粘附特性。

10. 发明申请

US20100219533A1 MULTILAYERED WIRING STRUCTURE, AND METHOD FOR MANUFACTURING MULTILAYERED WIRING 有权
标题翻译：多层布线结构及制造多层布线的方法
公开(公告)号：US20100219533A1
公开(公告)日：2010-09-02
申请号：US12278339
申请日：2007-02-06
申请人： Hiroto Ootake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
发明人： Hiroto Ootake , Masayoshi Tagami , Munehiro Tada , Yoshihiro Hayashi
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76808 , H01L21/76814 , H01L21/7682 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a wiring of the Damascene structure for preventing the TDDB withstand voltage degradation and for keeping the planarity to prevent the degradation of a focus margin. A trench wiring (213) is formed in an interlayer insulating film, which is composed of a silicon carbide-nitride film (205), a SiOCH film (206) and a silicon oxide film (207) [(e)]. The silicon oxide film (207) is etched at a portion adjacent to the wiring of a polished surface by dry etching or wet etching [(f)]. A silicon carbide-nitride film (SiCN) (214) is formed as a Cu cap film [(g)]. An interlayer insulating film is further formed thereon to form a conductive plug, a trench wiring and so on.
摘要翻译：提供了一种用于防止TDDB耐电压劣化并保持平面性以防止聚焦余量劣化的镶嵌结构的布线。沟槽布线（213）形成在由碳化硅 - 氮化物膜（SiO 2），SiOCH膜（206）和氧化硅膜（207）[（e）]组成的层间绝缘膜中。氧化硅膜（207）通过干蚀刻或湿蚀刻（f）]在与抛光表面的布线相邻的部分被蚀刻。形成碳化硅 - 氮化物膜（SiCN）（214）作为Cu帽膜[（g）]。还在其上形成层间绝缘膜以形成导电插塞，沟槽布线等。

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