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1. 发明申请

US20080031338A1 Interpolation frame generating method and interpolation frame generating apparatus 审中-公开
标题翻译：插值帧生成方法和插值帧生成装置
公开(公告)号：US20080031338A1
公开(公告)日：2008-02-07
申请号：US11882188
申请日：2007-07-31
申请人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04N7/28
CPC分类号： H04N19/521 , H04N19/51 , H04N19/577
摘要： According to one embodiment, an interpolation frame generating method includes detecting a motion vector of an object in input frame images by block matching processing between the input frame images, generating an interpolation frame by using the detected motion vector, and inserting the interpolation frame between the input image frames. The detecting includes calculating an absolute difference value between values of each pair of pixels located in same position in respective image blocks which are located in positions corresponding to each other on former and latter frames of the input frame images. A vector based on positions of a pair of blocks on the former and latter frames having minimum SAD indicating a cumulative sum value of the absolute difference values is selected as the motion vector. When the absolute difference value is larger than a predetermined value, the difference value is changed, and a possibility of erroneous detection of motion vector is reduced.
摘要翻译：根据一个实施例，内插帧生成方法包括通过输入帧图像之间的块匹配处理来检测输入帧图像中的对象的运动矢量，通过使用检测到的运动矢量生成内插帧，以及将插值帧插入到输入图像帧。该检测包括：计算位于相应位置的各个像素中的每对像素的值之间的绝对差值，所述各个图像块位于输入帧图像的前后帧上彼此对应的位置。选择基于具有指示绝对差值的累积和值的最小SAD的前一帧和后一帧上的一对块的位置的矢量作为运动矢量。当绝对差值大于预定值时，差值被改变，运动矢量错误检测的可能性降低。

2. 发明申请

US20080137747A1 INTERPOLATED FRAME GENERATING METHOD AND INTERPOLATED FRAME GENERATING APPARATUS 有权
标题翻译：插入式框架生成方法和内插框架生成装置
公开(公告)号：US20080137747A1
公开(公告)日：2008-06-12
申请号：US11950988
申请日：2007-12-05
申请人： MASAYA YAMASAKI , Yohei Hamakawa , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
发明人： MASAYA YAMASAKI , Yohei Hamakawa , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04N7/32
CPC分类号： H04N19/577 , H04N19/132 , H04N19/194 , H04N19/56 , H04N19/57 , H04N19/587
摘要： According to one embodiment, interpolated frame generating method of generating a new interpolated frame inserted between sequential frames, by using a plurality of input frame images, comprises first detecting of detecting at least one potential motion vector by block matching between the input frame images, using a first block of a fixed size, second detecting of detecting a motion vector by block matching between the input frame images, using a second block having a size variable within a range larger than that of the first block, and generating the interpolated frame by using the potential motion vector. The generating is generating the interpolated frame by using a potential motion vector closest to the motion vector detected by the second detecting among the potential motion vectors when a plurality of motion vectors are detected by the first detecting.
摘要翻译：根据一个实施例，通过使用多个输入帧图像来生成插入在连续帧之间的新内插帧的内插帧生成方法包括：首先通过使用输入帧图像之间的块匹配来检测至少一个潜在运动矢量，固定尺寸的第一块，使用具有大于第一块的尺寸变量的尺寸变量的第二块，通过使用第二块来生成内插帧，通过块输入帧图像之间的块匹配来检测运动矢量的第二检测潜在的运动矢量。当通过第一次检测检测到多个运动矢量时，该生成通过使用最靠近第二检测的运动矢量的潜在运动矢量在潜在的运动矢量中产生内插帧。

3. 发明申请

US20080063289A1 Frame interpolating circuit, frame interpolating method, and display apparatus 审中-公开
标题翻译：帧内插电路，帧插值方法和显示装置
公开(公告)号：US20080063289A1
公开(公告)日：2008-03-13
申请号：US11896857
申请日：2007-09-06
申请人： Hiroshi Yoshimura , Ko Sato , Keiko Hirayama , Yoshihiko Ogawa , Masaya Yamasaki , Yohei Hamakawa , Kenichi Douniwa
发明人： Hiroshi Yoshimura , Ko Sato , Keiko Hirayama , Yoshihiko Ogawa , Masaya Yamasaki , Yohei Hamakawa , Kenichi Douniwa
IPC分类号： G11B7/00
CPC分类号： G09G5/393 , G06T3/4007 , G09G5/363 , G09G2320/0261 , G09G2320/106 , H04N7/012 , H04N7/0132 , H04N7/014 , H04N19/51 , H04N19/513 , H04N19/577 , H04N19/61 , H04N19/80
摘要： According to one embodiment, a frame interpolating circuit including detecting unit which detects first frame image and second frame image from an input image signal and compares both the images with each other to detect a plurality of motion vectors in a plurality of blocks obtained by dividing the frame into blocks, filter unit which selects, of motion vectors in an upper block of one block and motion vectors in a right block of the one block, motion vector having vector value which is close to the values of the motion vectors and changes the values of the motion vectors in the one block into value different from the value of the motion vector by predetermined value (step), and interpolated frame generating unit which generates interpolated image on the basis of the motion vectors the values of which are changed and the first and second frame image.
摘要翻译：根据一个实施例，一种帧内插电路，包括检测单元，其从输入图像信号检测第一帧图像和第二帧图像，并将两个图像彼此进行比较，以检测多个块中的多个运动矢量，帧，块，用于选择一个块的上部块中的运动矢量的滤波器单元和一个块的右侧块中的运动矢量，运动矢量具有接近运动矢量的值的矢量值，并且改变值将一个块中的运动矢量的运动矢量转换为与运动矢量的值不同的预定值（步长）的值，以及内插帧生成单元，其基于其值被改变的运动矢量和第一和第二帧图像。

4. 发明申请

US20080063067A1 Frame interpolating circuit, frame interpolating method, and display apparatus 审中-公开
标题翻译：帧内插电路，帧插值方法和显示装置
公开(公告)号：US20080063067A1
公开(公告)日：2008-03-13
申请号：US11896985
申请日：2007-09-07
申请人： Keiko Hirayama , Masaya Yamasaki , Ko Sato , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Keiko Hirayama , Masaya Yamasaki , Ko Sato , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04B1/66
CPC分类号： H04N7/0132 , H04N5/144 , H04N19/51 , H04N19/513 , H04N19/55 , H04N19/577 , H04N19/61 , H04N19/80
摘要： According to one embodiment, there is provided a frame interpolating circuit including a detecting unit which detects a first frame image and a second frame image from an input image signal and compares both the images to detect a motion vector, a comparing unit which compares a size of the motion vector with a predetermined value, and a generating unit which, when the size of the motion vector is not more than the predetermined value as a result of comparison, generates and outputs an interpolated image between the first frame image and the second frame image on the basis of the detected motion vector and which, when the size of the motion vector is not less than the predetermined value as a result of comparison, reduces the size of the detected motion vector and generates the interpolated image between the first and second frame images.
摘要翻译：根据一个实施例，提供了一种帧内插电路，其包括检测单元，其从输入图像信号检测第一帧图像和第二帧图像，并比较两个图像以检测运动矢量;比较单元，以及生成单元，当所述运动矢量的大小作为比较的结果不大于所述预定值时，生成并输出所述第一帧图像和所述第二帧之间的内插图像基于检测到的运动矢量的图像，并且当运动矢量的大小作为比较的结果不小于预定值时，减小检测到的运动矢量的大小，并在第一和第二像素之间产生内插图像帧图像。

5. 发明授权

US08184703B2 Interpolated frame generating method and interpolated frame generating apparatus 有权
标题翻译：内插帧生成方法和内插帧生成装置
公开(公告)号：US08184703B2
公开(公告)日：2012-05-22
申请号：US11947263
申请日：2007-11-29
申请人： Yohei Hamakawa , Masaya Yamasaki , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Yohei Hamakawa , Masaya Yamasaki , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04N7/12 , H04N5/14 , G06K9/36
CPC分类号： H04N7/0132 , H04N7/014 , H04N19/533 , H04N19/57 , H04N19/577
摘要： According to one embodiment, an interpolated frame generator comprises first detector detects potential motion vector by block matching between input frame images, using first block of fixed size, second detector detects motion vector by block matching between the input frame images, using second block having fixed size larger than that of the first block, and generator generates interpolated frame by using the potential motion vector when first detector detects only one potential motion vector, and generates interpolated frame by using a potential motion vector closest to the motion vector detected by the second detector when first detector detects a plurality of motion vectors, wherein first detector includes extractor compares SAD of motion vector with SAD of motion vectors adjacent to the motion vector, and extracts potential motion vector having SAD smaller than any of the SAD of adjacent motion vectors, as a potential motion vector used in generator.
摘要翻译：根据一个实施例，内插帧生成器包括第一检测器，通过使用固定大小的第一块，通过输入帧图像之间的块匹配检测潜在运动矢量，第二检测器通过块输入帧图像之间的块匹配来检测运动矢量，使用具有固定并且当第一检测器仅检测到一个潜在的运动矢量时，发生器通过使用潜在运动矢量产生内插帧，并且通过使用最靠近由第二检测器检测到的运动矢量的电位运动矢量来生成内插帧当第一检测器检测到多个运动矢量时，其中第一检测器包括提取器将运动矢量的SAD与运动矢量相邻的运动矢量的SAD进行比较，并且提取具有比相邻运动矢量的任何SAD小的SAD的潜在运动矢量，如在发电机中使用的潜在运动矢量。

6. 发明授权

US08155198B2 Interpolated frame generating method and interpolated frame generating apparatus 有权
标题翻译：内插帧生成方法和内插帧生成装置
公开(公告)号：US08155198B2
公开(公告)日：2012-04-10
申请号：US11950988
申请日：2007-12-05
申请人： Masaya Yamasaki , Yohei Hamakawa , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Masaya Yamasaki , Yohei Hamakawa , Atsuo Shono , Hiroshi Yoshimura , Keiko Hirayama , Ko Sato , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04N7/12 , G06K9/36
CPC分类号： H04N19/577 , H04N19/132 , H04N19/194 , H04N19/56 , H04N19/57 , H04N19/587
摘要： According to one embodiment, interpolated frame generating method of generating a new interpolated frame inserted between sequential frames, by using a plurality of input frame images, comprises first detecting of detecting at least one potential motion vector by block matching between the input frame images, using a first block of a fixed size, second detecting of detecting a motion vector by block matching between the input frame images, using a second block having a size variable within a range larger than that of the first block, and generating the interpolated frame by using the potential motion vector. The generating is generating the interpolated frame by using a potential motion vector closest to the motion vector detected by the second detecting among the potential motion vectors when a plurality of motion vectors are detected by the first detecting.
摘要翻译：根据一个实施例，通过使用多个输入帧图像来生成插入在连续帧之间的新内插帧的内插帧生成方法包括：首先通过使用输入帧图像之间的块匹配来检测至少一个潜在运动矢量，固定尺寸的第一块，使用具有大于第一块的尺寸变量的尺寸变量的第二块，通过使用第二块来生成内插帧，通过块输入帧图像之间的块匹配来检测运动矢量的第二检测潜在的运动矢量。当通过第一次检测检测到多个运动矢量时，该生成通过使用最靠近第二检测的运动矢量的潜在运动矢量在潜在的运动矢量中产生内插帧。

7. 发明申请

US20080063308A1 Frame interpolating circuit, frame interpolating method, and display apparatus 审中-公开
标题翻译：帧内插电路，帧插值方法和显示装置
公开(公告)号：US20080063308A1
公开(公告)日：2008-03-13
申请号：US11896854
申请日：2007-09-06
申请人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： G06K9/32
CPC分类号： H04N7/0132 , H04N5/144 , H04N19/117 , H04N19/132 , H04N19/17 , H04N19/513 , H04N19/55 , H04N19/577 , H04N19/587 , H04N19/85
摘要： According to one embodiment, there is provided a frame interpolating circuit including a detecting unit which compares a first frame image and a second frame image from an input image signal with each other and detects a plurality of motion vectors in the frames, a limiting unit which limits values of the detected motion vectors in predetermined regions in the frames to a value equal to or smaller than a predetermined value, and an interpolated frame generating unit which generates and outputs an interpolated frame on the basis of the plurality of motion vectors from the detecting unit, the motion vectors the values of which are limited and which are output from the limiting unit, and the first frame image and the second frame image.
摘要翻译：根据一个实施例，提供了一种帧内插电路，包括：检测单元，其将来自输入图像信号的第一帧图像和第二帧图像彼此进行比较，并检测帧中的多个运动矢量;限制单元，将帧中的预定区域中检测到的运动矢量的值限制为等于或小于预定值的值;以及内插帧生成单元，其基于来自检测的多个运动矢量生成并输出内插帧单位，其值被限制并且从限制单元输出的运动矢量，以及第一帧图像和第二帧图像。

8. 发明申请

US20080025403A1 Interpolation frame generating method and interpolation frame forming apparatus 审中-公开
标题翻译：插值帧生成方法和插值帧形成装置
公开(公告)号：US20080025403A1
公开(公告)日：2008-01-31
申请号：US11882187
申请日：2007-07-31
申请人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
发明人： Ko Sato , Masaya Yamasaki , Keiko Hirayama , Hiroshi Yoshimura , Yohei Hamakawa , Kenichi Douniwa , Yoshihiko Ogawa
IPC分类号： H04N7/28
CPC分类号： H04N5/144 , H04N7/0127 , H04N7/014 , H04N19/51 , H04N19/521 , H04N19/533 , H04N19/57 , H04N19/577 , H04N19/587
摘要： According to one embodiment, an interpolation frame generating method performs motion detection processing using two blocks having different sizes, and adopts a motion vector detected by a smaller block under normal conditions. When a plurality of reliable motion vector candidates are detected in vector detection using the smaller block, a vector detected by a larger block is referred to, and a motion vector which is closest to the motion vector detected with the larger block among the motion vectors detected with the smaller block is adopted as a motion vector of the block to be used for generating an interpolation frame.
摘要翻译：根据一个实施例，内插帧生成方法使用具有不同尺寸的两个块来执行运动检测处理，并且在正常条件下采用由较小块检测的运动矢量。当使用较小块的矢量检测中检测到多个可靠的运动矢量候选时，参考由较大块检测到的矢量，并且检测最接近运动矢量中检测到的运动矢量的运动矢量采用较小的块作为用于生成内插帧的块的运动矢量。

9. 发明申请

US20070296872A1 Line memory packaging apparatus and television receiver 有权
标题翻译：线内存包装设备和电视接收机
公开(公告)号：US20070296872A1
公开(公告)日：2007-12-27
申请号：US11812453
申请日：2007-06-19
申请人： Masaya Yamasaki , Yoshihiko Ogawa
发明人： Masaya Yamasaki , Yoshihiko Ogawa
IPC分类号： H04N9/64
CPC分类号： H04N5/14 , G11C7/1006 , G11C19/00 , H04N7/012 , H04N7/0132
摘要： According to one embodiment, using several random access memory components, these several RAM components are integrally driven to form a logical line memory. The number of using RAM components is reduced to the minimum, and thereby, hardware cost is reduced. A line memory forming apparatus comprises cascade-connected several RAM components, several line memories logically serial-connected in a manner that of the several RAM components, part of an output of the final-stage RAM component and part of an input of the first-stage RAM component are provided with several connection portions, and a controller controlling write address and read address of the several RAM components to drive the line memories.
摘要翻译：根据一个实施例，使用几个随机存取存储器组件，这些几个RAM组件被整体驱动以形成逻辑行存储器。使用RAM组件的数量减少到最小，从而降低了硬件成本。行存储器形成装置包括级联连接的几个RAM组件，以几个RAM组件的方式逻辑串行连接的几个行存储器，即最后级RAM组件的输出的一部分和第一级RAM组件的输入的一部分，具有多个连接部分的控制器RAM组件，以及控制多个RAM组件的写入地址和读取地址以驱动行存储器的控制器。

10. 发明授权

US08164693B2 Line memory packaging apparatus and television receiver 有权
标题翻译：线内存包装设备和电视接收机
公开(公告)号：US08164693B2
公开(公告)日：2012-04-24
申请号：US11812453
申请日：2007-06-19
申请人： Masaya Yamasaki , Yoshihiko Ogawa
发明人： Masaya Yamasaki , Yoshihiko Ogawa
IPC分类号： H04N9/64
CPC分类号： H04N5/14 , G11C7/1006 , G11C19/00 , H04N7/012 , H04N7/0132
摘要： According to one embodiment, using several random access memory components, these several RAM components are integrally driven to form a logical line memory. The number of using RAM components is reduced to the minimum, and thereby, hardware cost is reduced. A line memory forming apparatus comprises cascade-connected several RAM components, several line memories logically serial-connected in a manner that of the several RAM components, part of an output of the final-stage RAM component and part of an input of the first-stage RAM component are provided with several connection portions, and a controller controlling write address and read address of the several RAM components to drive the line memories.
摘要翻译：根据一个实施例，使用几个随机存取存储器组件，这些几个RAM组件被整体驱动以形成逻辑行存储器。使用RAM组件的数量减少到最小，从而降低了硬件成本。行存储器形成装置包括级联连接的几个RAM组件，以几个RAM组件的方式逻辑串行连接的几个行存储器，即最后级RAM组件的输出的一部分和第一级RAM组件的输入的一部分，具有多个连接部分的控制器RAM组件，以及控制多个RAM组件的写入地址和读取地址以驱动行存储器的控制器。

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