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1. 发明申请

US20060050564A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060050564A1
公开(公告)日：2006-03-09
申请号：US11219756
申请日：2005-09-07
申请人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
发明人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged: a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored in the sense amplifier circuit in data write or erase mode, wherein the pass/fall detection circuit comprises a data latch, into which a defective column isolation data is writable in accordance with a command input.
摘要翻译：非挥发性半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元;读出放大器电路，被配置为读取存储单元阵列的数据; 以及通过/失败检测电路，被配置为基于在数据写入或擦除模式中存储在读出放大器电路中的验证读取数据来检测写入或擦除完成，其中，通过/下降检测电路包括数据锁存器，缺陷列隔离数据可根据命令输入进行写入。

2. 发明授权

US07286400B2 Non-volatile semiconductor memory device with pass/fail detection circuit 有权
标题翻译：具有通过/失败检测电路的非易失性半导体存储器件
公开(公告)号：US07286400B2
公开(公告)日：2007-10-23
申请号：US11219756
申请日：2005-09-07
申请人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
发明人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored in the sense amplifier circuit in data write or erase mode, wherein the pass/fail detection circuit comprises a data latch, into which a defective column isolation data is writable in accordance with a command input.
摘要翻译：非挥发性半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元;读出放大器电路，被配置为读取存储单元阵列的数据; 以及通过/失败检测电路，被配置为基于在数据写入或擦除模式中存储在读出放大器电路中的验证读取数据来检测写入或擦除完成，其中，该通过/失败检测电路包括数据锁存器，缺陷列隔离数据可根据命令输入进行写入。

3. 发明授权

US07315915B2 Non-volatile semiconductor memory device and electric device with the same 失效
标题翻译：非易失性半导体存储器件和电器件相同
公开(公告)号：US07315915B2
公开(公告)日：2008-01-01
申请号：US10950416
申请日：2004-09-28
申请人： Yasuyuki Fukuda , Masatsugu Kojima , Kenichi Imamiya , Koji Hosono
发明人： Yasuyuki Fukuda , Masatsugu Kojima , Kenichi Imamiya , Koji Hosono
IPC分类号： G06F12/00
CPC分类号： G11C16/16
摘要： A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein, the cell array being divided into a plurality of blocks, each the block being divided into a plurality of sub-blocks each having one or plural and continuous pages; and a controller for controlling data erasure of the cell array in a way that each the sub-block serves as a unit of data erasure, wherein each the sub-block in the cell array stores the number of data erasure which is renewed by each data erasure, and the number of data erasure is limited for each the sub-block to a permissible maximum value stored in a certain block in the cell array.
摘要翻译：非挥发性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储器单元的单元阵列，所述单元阵列被划分为多个块，每个块被分成多个子块，每个子块具有一个或多个和连续的页面; 以及用于以每个子块用作数据擦除单位的方式控制单元阵列的数据擦除的控制器，其中单元阵列中的每个子块存储由每个数据更新的数据擦除次数并且将每个子块的数据擦除的数量限制为存储在单元阵列中的某个块中的允许的最大值。

4. 发明申请

US20050111259A1 Non-volatile semiconductor memory device and electric device with the same 失效
标题翻译：非易失性半导体存储器件和电器件相同
公开(公告)号：US20050111259A1
公开(公告)日：2005-05-26
申请号：US10950416
申请日：2004-09-28
申请人： Yasuyuki Fukuda , Masatsugu Kojima , Kenichi Imamiya , Koji Hosono
发明人： Yasuyuki Fukuda , Masatsugu Kojima , Kenichi Imamiya , Koji Hosono
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/16 , G11C7/00 , G11C11/34
CPC分类号： G11C16/16
摘要： A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein, the cell array being divided into a plurality of blocks, each the block being divided into a plurality of sub-blocks each having one or plural and continuous pages; and a controller for controlling data erasure of the cell array in a way that each the sub-block serves as a unit of data erasure, wherein each the sub-block in the cell array stores the number of data erasure which is renewed by each data erasure, and the number of data erasure is limited for each the sub-block to a permissible maximum value stored in a certain block in the cell array.
摘要翻译：非挥发性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储器单元的单元阵列，所述单元阵列被划分为多个块，每个块被分成多个子块，每个子块具有一个或多个和连续的页面; 以及用于以每个子块用作数据擦除单位的方式控制单元阵列的数据擦除的控制器，其中单元阵列中的每个子块存储由每个数据更新的数据擦除次数并且将每个子块的数据擦除的数量限制为存储在单元阵列中的某个块中的允许的最大值。

5. 发明授权

US08218373B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US08218373B2
公开(公告)日：2012-07-10
申请号：US12981063
申请日：2010-12-29
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

6. 发明申请

US20090080264A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20090080264A1
公开(公告)日：2009-03-26
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06 , G11C7/10 , G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

7. 发明授权

US07023741B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07023741B2
公开(公告)日：2006-04-04
申请号：US10318167
申请日：2002-12-13
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

8. 发明授权

US06977846B2 Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays 有权
公开(公告)号：US06977846B2
公开(公告)日：2005-12-20
申请号：US11046987
申请日：2005-01-31
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/3454
摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

9. 发明授权

US06907497B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06907497B2
公开(公告)日：2005-06-14
申请号：US10325714
申请日：2002-12-20
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
IPC分类号： G11C16/34 , G06F12/00
CPC分类号： G11C16/3463 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array, a data hold circuit, and a controller A program control function applies a program voltage to a selected memory cell to let data shift from a first logic state to a second logic state. A program verify control function verifies that a programmed data of the selected memory cell shifted to the second logic state. An erratic program verify control function checks that a threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state. An over-program verify control function checks that a threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，数据保持电路和控制器。程序控制功能将程序电压施加到所选择的存储器单元，以使数据从第一逻辑状态转换到第二逻辑状态。程序验证控制功能验证所选择的存储器单元的编程数据移动到第二逻辑状态。不稳定的程序验证控制功能检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值。过程程序验证控制功能检查所选择的存储单元的阈值电压移动到第二逻辑状态不超过设定为其上限的第四值。

10. 发明申请

US20110090742A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20110090742A1
公开(公告)日：2011-04-21
申请号：US12981163
申请日：2010-12-29
申请人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

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