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1. 发明申请

US20120243322A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20120243322A1
公开(公告)日：2012-09-27
申请号：US13489977
申请日：2012-06-06
申请人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

2. 发明申请

US20110090742A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20110090742A1
公开(公告)日：2011-04-21
申请号：US12981163
申请日：2010-12-29
申请人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

3. 发明申请

US20080175052A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080175052A1
公开(公告)日：2008-07-24
申请号：US12020981
申请日：2008-01-28
申请人： Koji HOSONO , Kenichi IMAMIYA , Hiroshi NAKAMURA
发明人： Koji HOSONO , Kenichi IMAMIYA , Hiroshi NAKAMURA
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.
摘要翻译：一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

4. 发明申请

US20130088922A1 SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF CHIPS AND CAPABILITY OF OUTPUTTING A BUSY SIGNAL 有权
公开(公告)号：US20130088922A1
公开(公告)日：2013-04-11
申请号：US13684407
申请日：2012-11-23
申请人： Hiroshi NAKAMURA , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi NAKAMURA , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

5. 发明申请

US20120140570A1 EEPROM with Increased Reading Speed 有权
标题翻译： EEPROM读取速度提高
公开(公告)号：US20120140570A1
公开(公告)日：2012-06-07
申请号：US13370064
申请日：2012-02-09
申请人： Hiroshi NAKAMURA , Kenichi IMAMIYA
发明人： Hiroshi NAKAMURA , Kenichi IMAMIYA
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C11/5621 , G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
摘要翻译：在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压Vread与电压Vsg1，Vsg2 在所选择的块中选择晶体管的选择栅极，从而使得可以实现高速读取，而不会导致插入在选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。选择晶体管的栅极。

6. 发明申请

US20090268526A1 SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：具有包括充电储存层的堆叠门和控制门的半导体存储器件及其控制方法
公开(公告)号：US20090268526A1
公开(公告)日：2009-10-29
申请号：US12406382
申请日：2009-03-18
申请人： Takeshi NAKANO , Hiroshi NAKAMURA , Koji HOSONO
发明人： Takeshi NAKANO , Hiroshi NAKAMURA , Koji HOSONO
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/08
摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
摘要翻译：半导体存储器件包括转移电路和控制电路。该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到其源极施加第二电压，并且其漏极连接到负载。控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

7. 发明公开

US20240277232A1 SCREENING APPARATUS FOR COLD SYNDROME-POSITIVE PEOPLE 审中-公开
公开(公告)号：US20240277232A1
公开(公告)日：2024-08-22
申请号：US18570779
申请日：2023-05-29
申请人： Hiroshi NAKAMURA
发明人： Hiroshi NAKAMURA
IPC分类号： A61B5/01 , A61B5/00
CPC分类号： A61B5/01 , A61B5/7246
摘要： A screening apparatus for cold syndrome-positive people includes an EIFU temperature measurer having right and left temperature measuring parts; a calculation unit of that calculates a difference value between a right and left EIFU temperatures measured with the right and left temperature measuring parts; an input unit of left/right discomfort to which right discomfort information and left discomfort information on discomfort in a right pharynx region and a left pharynx region perceived by the cold syndrome positive person are input; a calculation unit of left/right discomfort that calculates a degree of coincidence between the right discomfort information and the left discomfort information; an evaluation unit that outputs information of severity based on the calculated difference value and the degree of coincidence; and a reporting unit that notifies severity of the cold syndrome-positive person based on the information of severity.

8. 发明申请

US20120126835A1 FUEL SENSOR 失效
标题翻译：燃油传感器
公开(公告)号：US20120126835A1
公开(公告)日：2012-05-24
申请号：US13293405
申请日：2011-11-10
申请人： Hiroshi NAKAMURA
发明人： Hiroshi NAKAMURA
IPC分类号： G01R27/26
CPC分类号： G01N33/2852 , F02D2200/0611
摘要： An outer electrode projects from an opening, which is formed in an upper inner wall of a fuel passage, into the fuel passage. The fuel passage is adapted to conduct fuel generally in a horizontal direction. The outer electrode includes a fuel chamber in an inside of the outer electrode. An inner electrode is placed in the fuel chamber. A sensing circuit senses an alcohol concentration of the fuel based on an electrical property between the outer electrode and the inner electrode and a fuel temperature, which is sensed with a thermistor. The outer electrode includes a blocking portion and communication holes. The blocking portion limits intrusion of air bubbles, which flow along the upper inner wall of the fuel passage, into the communication holes.
摘要翻译：外部电极从形成在燃料通路的上部内壁的开口突出到燃料通路内。燃料通道适于一般沿水平方向传导燃料。外部电极在外部电极的内部包括燃料室。内部电极放置在燃料室中。感测电路基于外部电极和内部电极之间的电气特性以及用热敏电阻感测的燃料温度来感测燃料的醇浓度。外电极包括阻挡部分和连通孔。阻挡部分限制沿着燃料通道的上内壁流动的气泡的入侵到连通孔中。

9. 发明申请

US20100134178A1 BOOST CIRCUIT 有权
标题翻译：升压电路
公开(公告)号：US20100134178A1
公开(公告)日：2010-06-03
申请号：US12700192
申请日：2010-02-04
申请人： Hiroshi NAKAMURA
发明人： Hiroshi NAKAMURA
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/075 , H02M2003/077 , H02M2003/078
摘要： A boost circuit includes: first transistors connected in series between a voltage input node and a voltage output node to constitute a charge transfer circuit; and first capacitors, one ends of which are coupled to the respective connection nodes between the first transistors, the other ends thereof being applied with clocks with plural phases, wherein a gate of a certain stage transistor corresponding to one of the first transistors in the charge transfer circuit is coupled to a drain of another stage transistor corresponding to another one of the first transistors, which is disposed nearer to the voltage output node than the certain stage transistor and driven by the same phase clock as that of the certain stage transistor, the certain stage transistor being disposed nearer to the voltage output node than an initial stage transistor.
摘要翻译：升压电路包括：串联连接在电压输入节点和电压输出节点之间的第一晶体管，构成电荷转移电路; 以及第一电容器，其一端耦合到第一晶体管之间的相应连接节点，其另一端被施加具有多相的时钟，其中一个级晶体管的栅极对应于电荷中的第一晶体管之一传输电路耦合到与第一晶体管中的另一个晶体管相对应的另一级晶体管的漏极，第一晶体管的布置比特定级晶体管更靠近电压输出节点并且由与某一级晶体管相同的相位时钟驱动，特定级晶体管被设置为比初始级晶体管更靠近电压输出节点。

10. 发明申请

US20100110790A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100110790A1
公开(公告)日：2010-05-06
申请号：US12632203
申请日：2009-12-07
申请人： Tomoharu TANAKA , Hiroshi NAKAMURA , Toru TANZAWA
发明人： Tomoharu TANAKA , Hiroshi NAKAMURA , Toru TANZAWA
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

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