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1. 发明授权

US07035751B2 Nonvolatile memory microcomputer chip, and a method for testing the nonvolatile memory microcomputer chip 失效
标题翻译：非易失性存储器微计算机芯片，以及非易失性存储微计算机芯片的测试方法
公开(公告)号：US07035751B2
公开(公告)日：2006-04-25
申请号：US10694567
申请日：2003-10-28
申请人： Masatoshi Shinagawa , Akifumi Kawahara , Tetsuyuki Fukushima , Masakazu Kurata , Manabu Komiya
发明人： Masatoshi Shinagawa , Akifumi Kawahara , Tetsuyuki Fukushima , Masakazu Kurata , Manabu Komiya
IPC分类号： G06F19/00
CPC分类号： G11C29/1201 , G11C16/04 , G11C29/48 , G11C2029/0401 , G11C2029/2602
摘要： To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.
摘要翻译：为了提供一种非易失性存储微计算机，可以省略使用逻辑测试仪测试微型计算机单元的步骤，从而降低测试成本。存储器测试器将测试数据和期望数据提供给非易失性存储微计算机，并且非易失性存储器微计算机将它们存储在非易失性存储器中。随后，在接收到地址信号时，非易失性存储器基于与地址信号对应的测试数据和期望数据输出测试信号和期望信号。测试信号被提供给微计算机单元中的电路块，以驱动电路块。电路块返回测试结果信号，并将其与期望信号一起输出到存储器测试仪。存储器测试仪将测试结果信号和期望信号进行比较，以判断微机单元是否正常工作。

2. 发明申请

US20070133277A1 Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070133277A1
公开(公告)日：2007-06-14
申请号：US11602272
申请日：2006-11-21
申请人： Ken Kawai , Ryotaro Azuma , Akifumi Kawahara , Hitoshi Suwa , Hoshihide Haruyama
发明人： Ken Kawai , Ryotaro Azuma , Akifumi Kawahara , Hitoshi Suwa , Hoshihide Haruyama
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/16 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.
摘要翻译：存储单元晶体管阵列由在单个电荷累积部分中具有三个或更多个阈值电压分布状态的多个存储单元组成。程序序列控制电路将由多个数据值组成的数据组中包括的每条数据与三个或更多阈值电压分布的任何阈值电压分布相关联，以将数据存储在存储单元中，并且当重写数据时存储在存储单元中，用于在一个方向上用于数据存储的阈值电压分布，以执行数据重写操作。

3. 发明申请

US20140112054A1 CROSSPOINT NONVOLATILE MEMORY DEVICE AND FORMING METHOD THEREOF 有权
标题翻译： CROSSPOINT非易失性存储器件及其形成方法
公开(公告)号：US20140112054A1
公开(公告)日：2014-04-24
申请号：US13983314
申请日：2012-11-13
申请人： Kazuhiko Shimakawa , Akifumi Kawahara , Ryotaro Azuma , Ken Kawai
发明人： Kazuhiko Shimakawa , Akifumi Kawahara , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0002 , G11C13/0007 , G11C13/0038
摘要： A sense amplification circuit includes a sneak current compensating load current supply unit that selectively switches a load current among load currents having different current amounts and supplies the load current to a bit line selected by a column selection circuit. The sense amplification circuit outputs ‘L’ level when a current amount of the load current is more than a reference current amount, and outputs ‘H’ level when the current amount is less than the reference current amount. A control circuit adjusts the current amount to a predetermined current amount that causes the sense amplification circuit to output ‘H’ level. After the adjustment, the control circuit performs control to supply the load current having the predetermined current amount and controls the writing unit to keep the application until the sense amplification circuit outputs ‘L’ level.
摘要翻译：感测放大电路包括潜流补偿负载电流供应单元，其选择性地切换具有不同电流量的负载电流之间的负载电流，并将负载电流提供给由列选择电路选择的位线。当负载电流的当前量大于参考电流量时，感测放大电路输出“L”电平，当电流量小于基准电流量时，输出“H”电平。控制电路将电流量调整到使得感测放大电路输出“H”电平的预定电流量。在调整之后，控制电路进行控制以提供具有预定电流量的负载电流，并且控制写入单元以保持应用直到读出放大电路输出“L”电平。

4. 发明授权

US07408820B2 Nonvolatile semiconductor memory with virtual ground array 失效
标题翻译：具有虚拟接地阵列的非易失性半导体存储器
公开(公告)号：US07408820B2
公开(公告)日：2008-08-05
申请号：US11641951
申请日：2006-12-20
申请人： Takafumi Maruyama , Kazuyuki Kouno , Akifumi Kawahara , Yasuhiro Tomita
发明人： Takafumi Maruyama , Kazuyuki Kouno , Akifumi Kawahara , Yasuhiro Tomita
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/28
摘要： A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.
摘要翻译：虚拟接地阵列的非易失性半导体存储器用作位线，其中源和存储单元阵列中以列和列排列的非易失性存储单元的漏极的公共连接的公共连接用作位线，非易失性存储单元包括：获得在差分读出确定操作中用作参考的特性的参考单元; 以及在所述参考小区的一侧的相邻小区，所述相邻小区分享所述参考小区的源和漏极之一并且连接到连接到所述参考小区的字线，其中所述非易失性半导体存储器包括邻居当字线被激活以将参考单元设置为导通状态时，相邻单元在编程状态期间保持在非导通状态，将相邻单元设置为编程状态。

5. 发明申请

US20070183240A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20070183240A1
公开(公告)日：2007-08-09
申请号：US11641951
申请日：2006-12-20
申请人： Takafumi Maruyama , Kazuyuki Kouno , Akifumi Kawahara , Yasuhiro Tomita
发明人： Takafumi Maruyama , Kazuyuki Kouno , Akifumi Kawahara , Yasuhiro Tomita
IPC分类号： G11C7/02
CPC分类号： G11C16/0491 , G11C16/28
摘要： A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.
摘要翻译：虚拟接地阵列的非易失性半导体存储器用作位线，其中源和存储单元阵列中以列和列排列的非易失性存储单元的漏极的公共连接的公共连接用作位线，非易失性存储单元包括：获得在差分读出确定操作中用作参考的特性的参考单元; 以及在所述参考小区的一侧的相邻小区，所述相邻小区分享所述参考小区的源和漏极之一并且连接到连接到所述参考小区的字线，其中所述非易失性半导体存储器包括邻居当字线被激活以将参考单元设置为导通状态时，相邻单元在编程状态期间保持在非导通状态，将相邻单元设置为编程状态。

6. 发明授权

US5539700A Column selection circuit of semiconductor memory with transfer gate 失效
标题翻译：具有传输门的半导体存储器的列选择电路
公开(公告)号：US5539700A
公开(公告)日：1996-07-23
申请号：US489776
申请日：1995-06-13
申请人： Akifumi Kawahara , Toshiki Mori
发明人： Akifumi Kawahara , Toshiki Mori
IPC分类号： G11C11/41 , C21C5/40 , G11C7/10 , G11C8/18 , G11C11/407 , G11C11/409 , G11C11/417 , G11C7/00
CPC分类号： G11C7/1006 , G11C8/18
摘要： A column selection circuit of a semiconductor memory includes a plurality of transfer gates each of which is arranged between each sense amplifier and each column select gate for gating each column to an internal bus according to a difference between a potential of each bit line and a precharge potential of each data bus.
摘要翻译：半导体存储器的列选择电路包括多个传输门，每个传输门被布置在每个读出放大器和每个列选择栅之间，用于根据每个位线的电位与预充电之间的差值将每列门控到内部总线每个数据总线的潜力。

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