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1. 发明申请

US20110055463A1 SEMICONDUCTOR DEVICE AND DRIVING METHOD THE SAME 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20110055463A1
公开(公告)日：2011-03-03
申请号：US12872254
申请日：2010-08-31
申请人： Masato ISHII , Yasuyuki TAKAHASHI , Takuro OHMARU , Hidetomo KOBAYASHI , Yutaka SHIONOIRI
发明人： Masato ISHII , Yasuyuki TAKAHASHI , Takuro OHMARU , Hidetomo KOBAYASHI , Yutaka SHIONOIRI
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/1433 , G06F2212/178
摘要： It is an object to prevent miswriting by radio in a relatively easy way in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication, in particular, in an RFID tag provided with an OTP memory or a write-once memory. Alternatively, it is an object to prevent data from being tampered. Further alternatively, it is an object to inhibit access to a memory in a relatively easy way and to inhibit reading of data in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication. In a semiconductor device including a control circuit and an OTP memory, a memory includes at least a sector for preventing additional writing and an information sector. When data for preventing additional writing is written to the sector for preventing additional writing and information is written to the information sector which is electrically connected to the sector for preventing additional writing, additional writing to the information sector to which the information is written is impossible.
摘要翻译：本发明的目的是在能够通过无线通信进行数据通信（接收/发送）的半导体装置中以相对容易的方式防止在无线电中的错误写入，特别是在设置有OTP存储器或一次写入的RFID标签中记忆。或者，其目的是防止数据被篡改。进一步地，本发明的目的是以相对简单的方式禁止对存储器的访问，并且禁止通过无线通信进行数据通信（接收/发送）的半导体装置中的数据的读取。在包括控制电路和OTP存储器的半导体器件中，存储器至少包括用于防止额外写入的扇区和信息扇区。当防止附加写入的数据被写入扇区以防止附加写入时，信息被写入电连接到扇区的信息扇区以防止附加写入，对写入信息的信息扇区的附加写入是不可能的。

2. 发明申请

US20120293203A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120293203A1
公开(公告)日：2012-11-22
申请号：US13471879
申请日：2012-05-15
申请人： Takuro OHMARU , Yutaka SHIONOIRI
发明人： Takuro OHMARU , Yutaka SHIONOIRI
IPC分类号： H03K19/177
CPC分类号： H01L27/105 , H03K19/1776 , H03K19/17764 , H03K19/17772
摘要： A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor.
摘要翻译：即使停止供给电源电位，也可以进行数据保持的可编程模拟装置。可编程电路包括并联或串联连接的单位单元，并且每个单位单元包括模拟元件。每个单电池的导通状态在导通状态和断开状态之间变化。每个单电池包括作为单位电池的开关的具有足够低的截止电流的第一晶体管和第二晶体管，第二晶体管的栅电极电连接到第一晶体管的源电极或漏电极晶体管。单电池的导通状态由第二晶体管的栅电极的电位来控制，即使在没有供电的情况下，由于第一晶体管的低截止电流也可以保持该电位。

3. 发明申请

US20120043953A1 POWER SUPPLY CIRCUIT 有权
标题翻译：电源电路
公开(公告)号：US20120043953A1
公开(公告)日：2012-02-23
申请号：US13206819
申请日：2011-08-10
申请人： Takuro OHMARU
发明人： Takuro OHMARU
IPC分类号： G05F1/618
CPC分类号： H02M3/156
摘要： In the case where the duty cycle of the PWM signal exists and the duty cycle of the PWM signal is constant for a certain period, a feedback control circuit is operated intermittently with the duty cycle fixed. Specifically, a power supply circuit includes an A/D converter circuit for forming a digital value based on an analog value obtained by monitoring an output voltage based on a reference voltage, a digital filter circuit for smoothing the digital value, a PWM signal generator circuit for generating a PWM signal based on an output value of the digital filter circuit, and an operation mode control circuit for controlling a circuit operation mode based on the duty cycle of the PWM signal.
摘要翻译：在存在PWM信号的占空比并且PWM信号的占空比在一定时间内恒定的情况下，反馈控制电路在占空比固定的情况下间歇地操作。具体地说，电源电路包括A / D转换器电路，用于基于通过基于参考电压监视输出电压获得的模拟值形成数字值，用于平滑数字值的数字滤波器电路，PWM信号发生器电路用于基于数字滤波器电路的输出值产生PWM信号;以及操作模式控制电路，用于基于PWM信号的占空比来控制电路操作模式。

4. 发明申请

US20110259420A1 PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：光电转换装置及其制造方法
公开(公告)号：US20110259420A1
公开(公告)日：2011-10-27
申请号：US13087714
申请日：2011-04-15
申请人： Shunpei YAMAZAKI , Hajime KIMURA , Yoshiaki ITO , Takuro OHMARU
发明人： Shunpei YAMAZAKI , Hajime KIMURA , Yoshiaki ITO , Takuro OHMARU
IPC分类号： H01L31/0203
CPC分类号： H01L31/202 , C23C14/08 , C23C14/34 , H01L21/02422 , H01L21/02538 , H01L21/02554 , H01L21/02565 , H01L21/0262 , H01L21/02672 , H01L31/0296 , H01L31/0304 , H01L31/0312 , H01L31/03685 , H01L31/03762 , H01L31/0392 , H01L31/075 , H01L31/1816 , H02S40/32 , Y02E10/544 , Y02E10/545 , Y02E10/548 , Y02P70/521
摘要： It is an object to reduce the region of a photoelectric conversion element which light does not reach, to suppress deterioration of power generation efficiency, and to suppress manufacturing cost of a voltage conversion element. The present invention relates to a transmissive photoelectric conversion device which includes a photoelectric conversion element including an n-type semiconductor layer, an intrinsic semiconductor layer, and a p-type semiconductor layer; a voltage conversion element which is overlapped with the photoelectric conversion element and which includes an oxide semiconductor film for a channel formation region; and a conductive element which electrically connects the photoelectric conversion element and the voltage conversion element. The photoelectric conversion element is a solar cell. The voltage conversion element includes a transistor having a channel formation region including an oxide semiconductor film. The voltage conversion element is a DC-DC converter.
摘要翻译：本发明的目的是减少不能到达的光电转换元件的区域，以抑制发电效率的劣化，并且抑制电压转换元件的制造成本。本发明涉及一种透射光电转换装置，其包括：包括n型半导体层，本征半导体层和p型半导体层的光电转换元件; 电压转换元件，其与光电转换元件重叠并且包括用于沟道形成区域的氧化物半导体膜; 以及电连接光电转换元件和电压转换元件的导电元件。光电转换元件是太阳能电池。电压转换元件包括具有包括氧化物半导体膜的沟道形成区的晶体管。电压转换元件是DC-DC转换器。

5. 发明申请

US20120306467A1 DC-DC CONVERTER, POWER SOURCE CIRCUIT, AND SEMICONDUCTOR DEVICE 有权
标题翻译： DC-DC转换器，电源电路和半导体器件
公开(公告)号：US20120306467A1
公开(公告)日：2012-12-06
申请号：US13477588
申请日：2012-05-22
申请人： Takuro OHMARU
发明人： Takuro OHMARU
IPC分类号： G05F1/46
CPC分类号： H02M3/157
摘要： A DC-DC converter includes a control circuit, a switching element, and a constant-voltage generation portion which generates an output voltage on the basis of an input voltage supplied through the switching element. The control circuit includes AD converters which convert the input voltage and the output voltage, a signal processing circuit, a pulse modulation circuit, and a power supply control circuit which controls supply of a power supply voltage to the signal processing circuit in accordance with digital values of the input voltage and the output voltage. The signal processing circuit determines the duty ratio in accordance with the digital value of the output voltage, and the pulse modulation circuit controls the switching element. The signal processing circuit includes a memory device including a memory element, a capacitor for storing data of the memory element, and a transistor for controlling charge in the capacitor. The transistor includes an oxide semiconductor.
摘要翻译： DC-DC转换器包括控制电路，开关元件和恒定电压产生部分，其根据通过开关元件提供的输入电压产生输出电压。控制电路包括转换输入电压和输出电压的AD转换器，信号处理电路，脉冲调制电路和电源控制电路，其根据数字值控制向信号处理电路的电源电压供应的输入电压和输出电压。信号处理电路根据输出电压的数字值来确定占空比，并且脉冲调制电路控制开关元件。信号处理电路包括存储器件，其包括存储元件，用于存储存储元件的数据的电容器和用于控制电容器中的电荷的晶体管。晶体管包括氧化物半导体。

6. 发明申请

US20110254095A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110254095A1
公开(公告)日：2011-10-20
申请号：US13083642
申请日：2011-04-11
申请人： Koichiro KAMATA , Yoshiaki ITO , Takuro OHMARU
发明人： Koichiro KAMATA , Yoshiaki ITO , Takuro OHMARU
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/1225 , H01L21/76254 , H01L27/1251 , H01L27/127 , H01L29/66772
摘要： An object is to reduce the number of manufacturing steps of a semiconductor device, to improve yield of a semiconductor device, or to reduce manufacturing cost of a semiconductor device. One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes, over a substrate, a first transistor having a single crystal semiconductor layer in a channel formation region, a second transistor that is isolated from the first transistor with an insulating layer positioned therebetween and has an oxide semiconductor layer in a channel formation region, and a diode having a single crystal semiconductor layer and a oxide semiconductor layer.
摘要翻译：目的是减少半导体器件的制造步骤的数量，以提高半导体器件的产量，或者降低半导体器件的制造成本。本发明的一个实施例涉及半导体器件和制造半导体器件的方法。半导体器件在衬底上包括在沟道形成区域中具有单晶半导体层的第一晶体管，与第一晶体管隔离的第二晶体管，绝缘层位于其间并具有沟道形成中的氧化物半导体层区域，以及具有单晶半导体层和氧化物半导体层的二极管。

7. 发明申请

US20120271984A1 MEMORY ELEMENT AND MEMORY DEVICE 审中-公开
标题翻译：存储元件和存储器件
公开(公告)号：US20120271984A1
公开(公告)日：2012-10-25
申请号：US13444177
申请日：2012-04-11
申请人： Takuro OHMARU , Yukio MAEHASHI
发明人： Takuro OHMARU , Yukio MAEHASHI
IPC分类号： G06F12/00
CPC分类号： G11C11/412 , G11C14/0054
摘要： An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.
摘要翻译：目的是提供一种具有新颖结构的存储元件，其中即使在电源停止之后也可以保持数据。存储元件包括锁存电路，第一选择电路，第二选择电路，第一非易失性存储器电路和第二非易失性存储器电路。第一非易失性存储器电路和第二非易失性存储器电路各自包括晶体管和电容器。包括在第一非易失性存储器电路和第二非易失性存储器电路中的晶体管是在氧化物半导体膜中形成沟道的晶体管。这种晶体管的截止电流非常小。数据被输入到晶体管和电容器彼此连接的节点之后，晶体管截止，即使电源电压停止，数据也能长时间保持。

8. 发明申请

US20110254523A1 POWER SOURCE CIRCUIT 有权
标题翻译：电源电路
公开(公告)号：US20110254523A1
公开(公告)日：2011-10-20
申请号：US13082459
申请日：2011-04-08
申请人： Yoshiaki ITO , Takuro OHMARU
发明人： Yoshiaki ITO , Takuro OHMARU
IPC分类号： G05F1/10
CPC分类号： H02M3/157 , G05F1/00 , G09G3/10
摘要： An object is to reduce degradation of circuit operation and to reduce the area of the entire circuit. A power source circuit is provided with a first terminal to which first voltage is input; a second terminal to which second voltage is input; a comparator being connected to the first terminal and the second terminal and comparing the first voltage and the second voltage; a digital circuit averaging, integrating, and digital pulse width modulating a first digital signal output from the comparator; a PWM output driver amplifying a second digital signal output from the digital circuit; and a smoothing circuit smoothing the amplified second digital signal.
摘要翻译：目的是减少电路运行的恶化并减少整个电路的面积。电源电路设置有输入第一电压的第一端子; 输入第二电压的第二端子; 比较器连接到第一端子和第二端子，并且比较第一电压和第二电压; 数字电路对从比较器输出的第一数字信号进行平均，积分和数字脉宽调制; PWM输出驱动器，放大从数字电路输出的第二数字信号; 以及使放大的第二数字信号平滑的平滑电路。

9. 发明申请

US20100080074A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100080074A1
公开(公告)日：2010-04-01
申请号：US12567975
申请日：2009-09-28
申请人： Takuro OHMARU , Tomoaki ATSUMI , Toshihiko SAITO
发明人： Takuro OHMARU , Tomoaki ATSUMI , Toshihiko SAITO
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C16/3459 , G11C16/349 , G11C29/4401 , G11C29/808 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402
摘要： Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.
摘要翻译：要实现具有纠正缺陷的简单快速的存储器访问。在半导体存储器件的备用存储器中，提供存储修正缺陷数量的冗余存储单元阵列。当接收到来自外部的信号时，信号被切换到冗余存储单元阵列，并且判断校正缺陷的数量。然后，基于判断结果，确定不良存储单元的判断继续，或判断结束，将数据写入主存储单元。通过提供存储校正缺陷数量的冗余存储单元阵列，可以以这种方式快速观察校正缺陷的状态。

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