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1. 发明授权

US09070743B2 Semiconductor memory and manufacturing method of the same 有权
标题翻译：半导体存储器及其制造方法相同
公开(公告)号：US09070743B2
公开(公告)日：2015-06-30
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L29/788 , H01L21/762 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

2. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

3. 发明申请

US20130062682A1 SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20130062682A1
公开(公告)日：2013-03-14
申请号：US13428430
申请日：2012-03-23
申请人： Masato ENDO , Yoshiko Kato
发明人： Masato ENDO , Yoshiko Kato
IPC分类号： H01L29/792 , H01L21/76
CPC分类号： H01L27/11524 , H01L27/11546
摘要： According to one embodiment, a semiconductor memory includes a memory cell provided in a first active area surrounded with a first isolation insulating film, a first transistor provided in a second active area surrounded with a second isolation insulating film, a shield gate electrode on the second isolation insulating film. The bottom surface of the shield gate electrode is positioned more closely to a semiconductor substrate side as compared with the highest upper surface of the second isolation insulating film.
摘要翻译：根据一个实施例，半导体存储器包括设置在由第一隔离绝缘膜包围的第一有源区域中的存储单元，设置在被第二隔离绝缘膜包围的第二有源区域中的第一晶体管，第二隔离绝缘膜上的屏蔽栅电极隔离绝缘膜。与第二隔离绝缘膜的最高上表面相比，屏蔽栅电极的底表面更靠近半导体衬底侧。

4. 发明授权

US08294221B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08294221B2
公开(公告)日：2012-10-23
申请号：US12952637
申请日：2010-11-23
申请人： Yoshiko Kato , Hiroyuki Kutsukake , Masayuki Ichige
发明人： Yoshiko Kato , Hiroyuki Kutsukake , Masayuki Ichige
IPC分类号： H01L21/70
CPC分类号： H01L27/11521 , H01L27/11519
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cell blocks, a plurality of first wirings, a plurality of second wirings, and a contact. Each of the memory cell blocks includes a plurality of memory cell units. Each of the plurality of memory cell units includes a plurality of memory cells and is provided in a first direction at a prescribed spacing. The plurality of memory cell blocks is arranged in a second direction intersecting with the first direction. The plurality of first wirings extends in the second direction and is provided in the first direction at a prescribed spacing. The plurality of second wirings is provided at least one of above and below the first wiring. The contact is provided at both end portions of the second wiring in the second direction and connects the first wiring to the second wiring. A width dimension of the second wiring along the first direction is larger than a width dimension of the first wiring along the first direction.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储器单元块，多个第一布线，多个第二布线和一个触点。每个存储单元块包括多个存储单元单元。多个存储单元单元中的每一个包括多个存储单元，并且以规定间隔沿第一方向设置。多个存储单元块被布置在与第一方向交叉的第二方向上。多个第一配线在第二方向上延伸并且以规定间隔沿第一方向设置。多个第二布线被设置在第一布线的上方和下方中的至少一个。在第二方向的第二配线的两端设置接点，将第一配线连接到第二配线。沿着第一方向的第二布线的宽度尺寸大于沿着第一方向的第一布线的宽度尺寸。

5. 发明申请

US20110019469A1 SEMICONDUCTOR MEMORY 失效
标题翻译：半导体存储器
公开(公告)号：US20110019469A1
公开(公告)日：2011-01-27
申请号：US12894256
申请日：2010-09-30
申请人： Yoshiko Kato , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： G11C11/34
CPC分类号： G11C5/025 , G11C16/0483
摘要： A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line.
摘要翻译：半导体存储器包括具有存储单元的存储单元阵列区域，与存储单元阵列区域相邻的字线接触区域，跨过存储单元阵列区域排列的字线和字线接触区域，字线接触区域中的字线，以及经由接触孔连接到字线的字线驱动器。接触孔的尺寸大于字线的宽度，并且接触孔的最低部分存在于比字线的顶表面低的位置，并且高于字线的底表面。

6. 发明申请

US20090275181A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090275181A1
公开(公告)日：2009-11-05
申请号：US12500912
申请日：2009-07-10
申请人： Yoshiko Kato , Shigeru Ishibashi , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Shigeru Ishibashi , Mitsuhiro Noguchi
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823857 , H01L21/823892
摘要： A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.
摘要翻译：根据本发明的实施例的半导体器件包括第一导电类型的第一半导体区域，形成在第一半导体区域中的第二导电类型的第一MIS晶体管，第二导电类型的第二半导体区域，以及形成在第二半导体区域中的第一导电类型的第二MIS晶体管。第一MIS晶体管的第一栅极绝缘层比第二MIS晶体管的第二栅极绝缘层厚，并且第二MIS晶体管的沟道区中的第一导电类型的杂质的轮廓具有峰值。

7. 发明申请

US20070170589A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20070170589A1
公开(公告)日：2007-07-26
申请号：US11624386
申请日：2007-01-18
申请人： Yoshiko Kato , Shigeru Ishibashi , Mitsuhiro Noguchi , Toshiki Hisada
发明人： Yoshiko Kato , Shigeru Ishibashi , Mitsuhiro Noguchi , Toshiki Hisada
IPC分类号： H01L23/52 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11529
摘要： A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.
摘要翻译：根据本发明的半导体集成电路包括由元件构成的单元阵列，具有布置在单元阵列上的线和空间的图案的导线，形成在导线上方的连接线，以及将导线到连接线。导线的一端侧从导体线之一顺序离开电池阵列的端部，接触孔布置在导线的一端侧，接触孔的尺寸较大比导线的宽度大。

8. 发明授权

US4879295A N-tetrazolyl thiazolecarboxyamide derivatives and their use 失效
标题翻译： N-四唑基噻唑基酰胺衍生物及其用途
公开(公告)号：US4879295A
公开(公告)日：1989-11-07
申请号：US98015
申请日：1987-09-17
申请人： Junji Yoshinaga , Takeshi Shoyaki , Takao Kakita , Hiromi Ozeki , Nobuko Sugimoto , Yoshiko Kato
发明人： Junji Yoshinaga , Takeshi Shoyaki , Takao Kakita , Hiromi Ozeki , Nobuko Sugimoto , Yoshiko Kato
IPC分类号： C07D417/12 , C07D417/14
CPC分类号： C07D417/12 , C07D417/14
摘要： Compounds of the formula: ##STR1## wherein A is a C.sub.1-6 alkyl group, an aryl group which is unsubstituted or substituted with at least one substituent selected from hydroxy, alkoxy, aryl-(C.sub.1-6)alkoxy, C.sub.1-6 alkylcarbonyloxy, halo-(C.sub.1-6)alkyl, halogen, nitro and amino,or 5- or 6-membered heterocyclic group containing at least one hetero atom selected from oxygen, nitrogen and sulfur, or a condensed heterocyclic group consisting of a heterocycle as defined above and a benzene nucleus,these two heterocyclic groups being unsubstituted or substituted with at least one substituent selected from hydroxy, C.sub.1-6 alkyl and halogen, and R is hydrogen or a C.sub.1-6 alkyl group,or a pharmaceutically acceptable salt thereof are nobel and useful as antiallergic.

9. 发明授权

US09035370B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09035370B2
公开(公告)日：2015-05-19
申请号：US13415010
申请日：2012-03-08
申请人： Yoshiko Kato , Hiroyuki Kutsukake
发明人： Yoshiko Kato , Hiroyuki Kutsukake
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/11558 , H01L27/11531
摘要： A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side.
摘要翻译：一种半导体器件，包括：半导体衬底; 第一导电类型井和第二导电类型井; 第一个活跃区域; 第二个活跃区域; 第一阱接触层; 多个第一源极/漏极层; 第一栅极绝缘膜; 第一栅电极; 第二阱接触层; 多个第二源极/漏极层; 第二栅绝缘膜; 和第二栅电极。第一阱接触层在一个方向上的一个端部的第一有源区域中形成。第一有效区域和第二有源区域中的每一个中的一端部分彼此相同。

10. 发明授权

US08698204B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08698204B2
公开(公告)日：2014-04-15
申请号：US13226763
申请日：2011-09-07
申请人： Hiroyuki Kutsukake , Yoshiko Kato
发明人： Hiroyuki Kutsukake , Yoshiko Kato
IPC分类号： H01L27/118 , H01L27/108 , H01L29/76 , H01L23/52 , H01L23/48 , H01L23/40
CPC分类号： H01L27/11524 , H01L27/11519 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor memory device includes a substrate, and device regions in the substrate to extend in a first direction. The device further includes select gates on the substrate to extend in a second direction, and a contact region provided between the select gates and including contact plugs on the respective device regions. The contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. The contact region includes the partial regions of at least two types whose values of N are different. Further, each of the contact plugs has a planar shape of an ellipse, and is arranged so that a major axis of the ellipse is tilted with respect to the first direction.
摘要翻译：在一个实施例中，半导体存储器件包括衬底以及衬底中沿第一方向延伸的器件区域。该装置还包括在基板上沿第二方向延伸的选择栅极以及设置在选择栅极之间并包括各个器件区域上的接触插塞的接触区域。接触区域包括部分区域，其中每个N个接触插塞设置在N个连续的器件区域上，以布置在不平行于第一和第二方向的直线上，其中N是2或更大的整数。接触区域包括N值不同的至少两种类型的部分区域。此外，每个接触插塞具有椭圆形的平面形状，并且被布置成使得椭圆的长轴相对于第一方向倾斜。

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