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1. 发明授权

US07763543B2 Method for manufacturing silicon carbide semiconductor apparatus 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US07763543B2
公开(公告)日：2010-07-27
申请号：US12289413
申请日：2008-10-28
申请人： Masatake Nagaya , Yuuichi Takeuchi , Katsuhiro Nagata
发明人： Masatake Nagaya , Yuuichi Takeuchi , Katsuhiro Nagata
IPC分类号： H01L21/311
CPC分类号： H01L21/8213 , H01L21/02013 , H01L21/02024 , H01L21/30625 , H01L29/1608 , Y10S438/931
摘要： A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.
摘要翻译：公开了一种制造碳化硅半导体器件的方法。根据该方法，在半导体基板的正面侧形成元件结构。半导体衬底的后表面在与平台的平坦表面平行的方向上被研磨或抛光。在研磨或抛光半导体衬底的后表面之后，在与背面平行的方向上研磨和抛光半导体衬底的前表面。

2. 发明申请

US20090124060A1 Method for manufacturing silicon carbide semiconductor apparatus 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US20090124060A1
公开(公告)日：2009-05-14
申请号：US12289413
申请日：2008-10-28
申请人： Masatake Nagaya , Yuuichi Takeuchi , Katsuhiro Nagata
发明人： Masatake Nagaya , Yuuichi Takeuchi , Katsuhiro Nagata
IPC分类号： H01L21/76 , H01L21/461
CPC分类号： H01L21/8213 , H01L21/02013 , H01L21/02024 , H01L21/30625 , H01L29/1608 , Y10S438/931
摘要： A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.
摘要翻译：公开了一种制造碳化硅半导体器件的方法。根据该方法，在半导体基板的正面侧形成元件结构。半导体衬底的后表面在与平台的平坦表面平行的方向上被研磨或抛光。在研磨或抛光半导体衬底的后表面之后，在与背面平行的方向上研磨和抛光半导体衬底的前表面。

3. 发明授权

US06710435B2 Semiconductor device arrangement and method of fabricating the same 有权
标题翻译：半导体器件布置及其制造方法
公开(公告)号：US06710435B2
公开(公告)日：2004-03-23
申请号：US10201158
申请日：2002-07-24
申请人： Masatake Nagaya , Toshiyuki Morishita
发明人： Masatake Nagaya , Toshiyuki Morishita
IPC分类号： H01L2302
CPC分类号： H01L25/0652 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device arrangement includes a plurality of three-dimensional semiconductor units. Each of the three-dimensional semiconductor units includes a semiconductor chip in a shape of a rectangular parallelepiped having six surfaces, and semiconductor devices formed on at least one among the six surfaces. The three-dimensional semiconductor units are mechanically connected and supported, and are electrically connected in a suitable way.
摘要翻译：半导体器件布置包括多个三维半导体单元。每个三维半导体单元包括具有六个表面的长方体形状的半导体芯片，以及形成在六个表面中的至少一个表面上的半导体器件。机械地连接和支撑三维半导体单元，并以合适的方式电连接。

4. 发明申请

US20110294403A1 WAFER PROCESSING METHOD, WAFER POLISHING APPARATUS, AND INGOT SLICING APPARATUS 失效
标题翻译：抛光加工方法，抛光抛光装置和切割装置
公开(公告)号：US20110294403A1
公开(公告)日：2011-12-01
申请号：US13114141
申请日：2011-05-24
申请人： Kyohei KOUTAKE , Hiromichi Morita , Fumiyoshi Kano , Tetsuji Yamaguchi , Sumitomo Inomata , Masatake Nagaya
发明人： Kyohei KOUTAKE , Hiromichi Morita , Fumiyoshi Kano , Tetsuji Yamaguchi , Sumitomo Inomata , Masatake Nagaya
IPC分类号： B24B1/00 , B28D1/02 , B24B49/16
CPC分类号： B28D5/022 , B28D5/0082 , H01L21/02008 , H01L21/02013
摘要： In a wafer processing method, an ingot is sliced into a wafer and the wafer is planarized by polishing a surface of the wafer. When the wafer is planarized, the wafer is disposed on a wafer holder and the wafer is rotated, a heat quantity is applied to a portion of the wafer so as to form a reformed layer at the portion of the wafer, and a polishing tool is brought into contact with the portion of wafer while rotating so as to polish the portion of the wafer.
摘要翻译：在晶片处理方法中，将锭切成晶片，通过抛光晶片的表面使晶片平坦化。当晶片平坦化时，将晶片设置在晶片保持器上并且晶片旋转，将热量施加到晶片的一部分，以在晶片的部分形成重整层，并且抛光工具在旋转的同时与晶片的该部分接触以抛光晶片的该部分。

5. 发明授权

US6060344A Method for producing a semiconductor substrate 有权
标题翻译：半导体基板的制造方法
公开(公告)号：US6060344A
公开(公告)日：2000-05-09
申请号：US136294
申请日：1998-08-19
申请人： Masaki Matsui , Masatake Nagaya , Hisayoshi Ohshima
发明人： Masaki Matsui , Masatake Nagaya , Hisayoshi Ohshima
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12 , H02L21/20
CPC分类号： H01L21/76264 , H01L21/76297 , H01L21/76275 , H01L21/76286
摘要： In a method for producing a semiconductor substrate completed through a bonding process for joining a semiconductor wafer to a support substrate by performing heat treatment thereto in a state in which the semiconductor wafer is closely joined to the support substrate, the method according to the present invention includes the following steps, i.e., a depositing process for depositing a poly-crystal semiconductor which covers all areas of a surface to be bonded on the surface of the semiconductor wafer; a heat treatment process for performing the heat treatment to the semiconductor wafer provided after the depositing process, during a predetermined time under a temperature equal to or higher than the heat treatment temperature at the bonding process; and a polishing process for flattening the surface of the poly-crystal semiconductor provided after the heat treatment process. After the above processes were performed in order, the bonding process is performed after the polishing process.
摘要翻译：在半导体基板的制造方法中，通过在将半导体晶片紧密接合到支撑基板的状态下对半导体晶片与支撑基板进行热处理的接合工序而完成，本发明的方法包括以下步骤，即，用于沉积覆盖半导体晶片表面上要接合的表面的所有区域的多晶半导体的沉积工艺; 在接合工序的等于或高于所述热处理温度的温度下的预定时间内对所述沉积工艺之后提供的所述半导体晶片进行热处理的热处理工艺; 以及用于使在热处理工艺之后提供的多晶半导体的表面变平的抛光工艺。在进行上述处理之后，在抛光处理之后进行接合处理。

6. 发明授权

US08758087B2 Wafer processing method, wafer polishing apparatus, and ingot slicing apparatus 失效
标题翻译：晶片加工方法，晶片抛光装置和锭切片装置
公开(公告)号：US08758087B2
公开(公告)日：2014-06-24
申请号：US13114141
申请日：2011-05-24
申请人： Kyohei Koutake , Hiromichi Morita , Fumiyoshi Kano , Tetsuji Yamaguchi , Sumitomo Inomata , Masatake Nagaya
发明人： Kyohei Koutake , Hiromichi Morita , Fumiyoshi Kano , Tetsuji Yamaguchi , Sumitomo Inomata , Masatake Nagaya
IPC分类号： B24B1/00 , B24B49/16
CPC分类号： B28D5/022 , B28D5/0082 , H01L21/02008 , H01L21/02013
摘要： In a wafer processing method, an ingot is sliced into a wafer and the wafer is planarized by polishing a surface of the wafer. When the wafer is planarized, the wafer is disposed on a wafer holder and the wafer is rotated, a heat quantity is applied to a portion of the wafer so as to form a reformed layer at the portion of the wafer, and a polishing tool is brought into contact with the portion of wafer while rotating so as to polish the portion of the wafer.
摘要翻译：在晶片处理方法中，将锭切成晶片，通过抛光晶片的表面使晶片平坦化。当晶片平坦化时，将晶片设置在晶片保持器上并且晶片旋转，将热量施加到晶片的一部分，以在晶片的部分形成重整层，并且抛光工具在旋转的同时与晶片的该部分接触以抛光晶片的该部分。

7. 发明授权

US5851846A Polishing method for SOI 失效
标题翻译： SOI抛光方法
公开(公告)号：US5851846A
公开(公告)日：1998-12-22
申请号：US576593
申请日：1995-12-21
申请人： Masaki Matsui , Masatake Nagaya , Akinari Fukaya , Hiroaki Himi
发明人： Masaki Matsui , Masatake Nagaya , Akinari Fukaya , Hiroaki Himi
IPC分类号： B24B49/14 , H01L21/02 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L27/12 , H01L21/66
CPC分类号： H01L21/31053
摘要： In a dielectric isolation substrate, an end point of a polishing process for selective polishing for forming an SOI layer is detected with a high precision. When polishing a wafer with a polishing pad, the temperature of a region of the polishing pad having polished the wafer at a position immediately thereafter is detected by a temperature sensor and the selective polishing process is ended by discriminating that the rate of variation in the detected temperature has changed from a positive to a negative state and then to a fixed saturated state.
摘要翻译：在绝缘隔离衬底中，以高精度检测用于形成SOI层的选择性抛光的抛光工艺的终点。当用抛光垫抛光晶片时，通过温度传感器检测在其后立即位置抛光晶片的抛光垫的区域的温度，并通过区分所检测到的变化率来结束选择性抛光工艺温度从正状态变为负状态，然后变为固定饱和状态。

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