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1. 发明授权

US08962470B2 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus 有权
标题翻译：凸起形成方法，半导体装置及其制造方法，基板处理装置和半导体制造装置
公开(公告)号：US08962470B2
公开(公告)日：2015-02-24
申请号：US12413898
申请日：2009-03-30
申请人： Masataka Mizukoshi , Yoshikatsu Ishizuki , Kanae Nakagawa , Keishiro Okamoto , Kazuo Teshirogi , Taiji Sakai
发明人： Masataka Mizukoshi , Yoshikatsu Ishizuki , Kanae Nakagawa , Keishiro Okamoto , Kazuo Teshirogi , Taiji Sakai
IPC分类号： H01L21/44 , H01L23/00 , H01L21/48
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/78 , H01L22/12 , H01L22/14 , H01L22/26 , H01L24/11 , H01L24/13 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05568 , H01L2224/05572 , H01L2224/05644 , H01L2224/11019 , H01L2224/1134 , H01L2224/11464 , H01L2224/11602 , H01L2224/11632 , H01L2224/1184 , H01L2224/13012 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/29111 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73104 , H01L2224/749 , H01L2224/75 , H01L2224/75252 , H01L2224/81075 , H01L2224/81801 , H01L2224/83192 , H01L2224/83193 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0781 , H01L2924/12042 , H01L2924/15788 , H01L2924/00014 , H01L2924/01028 , H01L2924/00 , H01L2224/29099
摘要： A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
摘要翻译：半导体基板通过抽吸固定到基板支撑台的支撑面的后表面。在这种情况下，半导体基板的厚度通过在后表面上的平坦化而被固定，并且后表面被强制地进入到通过吸力而不起伏的状态到支撑面，使得背面成为参考面用于正面的平坦化。在这种状态下，使用工具切割前表面上的Au突起和抗蚀剂掩模的表面层，从而使Au突起和抗蚀剂掩模平坦化，使得它们的表面变得连续平坦。这可以以低成本和高速代替CMP来平坦化形成在基板上的微细凸块的表面。

2. 发明申请

US20050161814A1 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus 审中-公开
标题翻译：凸起形成方法，半导体装置及其制造方法，基板处理装置和半导体制造装置
公开(公告)号：US20050161814A1
公开(公告)日：2005-07-28
申请号：US11083926
申请日：2005-03-21
申请人： Masataka Mizukoshi , Yoshikatsu Ishizuki , Kanae Nakagawa , Keishiro Okamoto , Kazuo Teshirogi , Taiji Sakai
发明人： Masataka Mizukoshi , Yoshikatsu Ishizuki , Kanae Nakagawa , Keishiro Okamoto , Kazuo Teshirogi , Taiji Sakai
IPC分类号： H01L21/48 , H01L21/60 , H01L23/48 , H01L23/485
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/78 , H01L22/12 , H01L22/14 , H01L22/26 , H01L24/11 , H01L24/13 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05568 , H01L2224/05572 , H01L2224/05644 , H01L2224/11019 , H01L2224/1134 , H01L2224/11464 , H01L2224/11602 , H01L2224/11632 , H01L2224/1184 , H01L2224/13012 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/29111 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73104 , H01L2224/749 , H01L2224/75 , H01L2224/75252 , H01L2224/81075 , H01L2224/81801 , H01L2224/83192 , H01L2224/83193 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0781 , H01L2924/12042 , H01L2924/15788 , H01L2924/00014 , H01L2924/01028 , H01L2924/00 , H01L2224/29099
摘要： A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
摘要翻译：半导体衬底（1）通过抽吸固定到衬底支撑台（11）的支撑面（11a）的后表面（1b）上。在这种情况下，半导体衬底（1）的厚度通过在后表面（1b）上的平坦化而被固定，并且后表面（1b）被强制地进入到通过抽吸而不起伏的状态到支撑面部（11a），使得背面（1b）成为用于使正面（1a）平坦化的基准面。在该状态下，使用工具（10）来切割前表面（1a）上的Au突起（2）和抗蚀剂掩模（12）的表面层，从而使Au突起（2）和抗蚀剂掩模 12），使其表面变得连续平坦。这可以以低成本和高速代替CMP来平坦化形成在基板上的微细凸块的表面。

3. 发明授权

US07648907B2 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
标题翻译：半导体装置，布线基板的形成方法以及基板处理装置
公开(公告)号：US07648907B2
公开(公告)日：2010-01-19
申请号：US11727004
申请日：2007-03-23
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L23/48
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
摘要翻译：制备具有平坦支撑面（201a）的基板支撑体（201），通过将布线形成面（1a）安装在支撑面（201a）上而将半导体基板（1）固定在基板支撑面（201）通过抽吸，例如通过真空抽吸。在这种情况下，布线形成表面（1a）通过抽吸附接到支撑表面（201a）而被强制地平坦化，因此布线形成表面（1a）成为用于平面化背面（1b）的参考平面。在这种状态下，通过机械研磨后表面（1b）以去除后表面（1b）的突出部分（12）来进行平面化处理。因此，基板（特别是半导体基板）的厚度的变化是均匀的，并且容易且廉价地实现高速平坦化，而没有诸如凹陷的缺点，并且对布线设计没有任何限制。

4. 发明授权

US07485962B2 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
标题翻译：半导体装置，布线基板的形成方法以及基板处理装置
公开(公告)号：US07485962B2
公开(公告)日：2009-02-03
申请号：US11097937
申请日：2005-04-01
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L23/48
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
摘要翻译：制备具有平坦支撑面（201a）的基板支撑体（201），通过将布线形成面（1a）安装在支撑面（201a）上而将半导体基板（1）固定在基板支撑面（201）通过抽吸，例如通过真空抽吸。在这种情况下，布线形成表面（1a）通过抽吸附接到支撑表面（201a）而被强制地平坦化，因此布线形成表面（1a）成为用于平面化背面（1b）的参考平面。在这种状态下，通过机械研磨后表面（1b）以去除后表面（1b）的突出部分（12）来进行平面化处理。因此，基板（特别是半导体基板）的厚度的变化是均匀的，并且容易且廉价地实现高速平坦化，而没有诸如凹陷的缺点，并且对布线设计没有任何限制。

5. 发明申请

US20050170640A1 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
标题翻译：半导体装置，布线基板的形成方法以及基板处理装置
公开(公告)号：US20050170640A1
公开(公告)日：2005-08-04
申请号：US11097937
申请日：2005-04-01
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L21/3105 , H01L21/321 , H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/68 , H01L21/768
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
摘要翻译：准备具有平坦支撑面（201a）的基板支撑体（201），通过将布线形成面（1a）安装在支撑面（13a）上而将半导体基板（1）固定在基板支撑面（201） 201a）通过抽吸，例如通过真空抽吸。在这种情况下，布线形成表面（1a）通过抽吸附接到支撑表面（201a）被强制地平坦化，因此布线形成表面（1a）成为用于平面化背面的参考平面（ 1 b）。在这种状态下，通过机械研磨后表面（1b）以研磨后表面（1b）的凸出部分（12）来进行平面化处理。因此，基板（特别是半导体基板）的厚度的变化是均匀的，并且容易且廉价地实现高速平坦化，而没有诸如凹陷的缺点，并且对布线设计没有任何限制。

6. 发明申请

US20070287282A1 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
标题翻译：半导体装置，布线基板的形成方法以及基板处理装置
公开(公告)号：US20070287282A1
公开(公告)日：2007-12-13
申请号：US11727004
申请日：2007-03-23
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L21/4763
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
摘要翻译：准备具有平坦支撑面（201a）的基板支撑体（201），通过将布线形成面（1a）安装在支撑面（13a）上而将半导体基板（1）固定在基板支撑面（201） 201a）通过抽吸，例如通过真空抽吸。在这种情况下，布线形成表面（1a）通过抽吸附接到支撑表面（201a）被强制地平坦化，因此布线形成表面（1a）成为用于平面化背面的参考平面（ 1 b）。在这种状态下，通过机械研磨后表面（1b）以研磨后表面（1b）的凸出部分（12）来进行平面化处理。因此，基板（特别是半导体基板）的厚度的变化是均匀的，并且容易且廉价地实现高速平坦化，而没有诸如凹陷的缺点，并且对布线设计没有任何限制。

7. 发明申请

US20070184646A1 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
公开(公告)号：US20070184646A1
公开(公告)日：2007-08-09
申请号：US11727003
申请日：2007-03-23
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L21/4763
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.

8. 发明授权

US07704856B2 Semiconductor device, wiring substrate forming method, and substrate processing apparatus 有权
公开(公告)号：US07704856B2
公开(公告)日：2010-04-27
申请号：US11727003
申请日：2007-03-23
申请人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
发明人： Kanae Nakagawa , Masataka Mizukoshi , Kazuo Teshirogi
IPC分类号： H01L21/30
CPC分类号： H01L21/4857 , H01L21/31058 , H01L21/32115 , H01L21/4846 , H01L21/6835 , H01L21/7684
摘要： A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.

9. 发明授权

US07432114B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07432114B2
公开(公告)日：2008-10-07
申请号：US11515994
申请日：2006-09-06
申请人： Kazuo Teshirogi , Yuzo Shimobeppu , Kazuhiro Yoshimoto , Yoshiaki Shinjo , Masataka Mizukoshi
发明人： Kazuo Teshirogi , Yuzo Shimobeppu , Kazuhiro Yoshimoto , Yoshiaki Shinjo , Masataka Mizukoshi
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/563 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/544 , H01L24/11 , H01L24/12 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/90 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2221/68322 , H01L2221/68336 , H01L2221/68354 , H01L2223/54426 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05572 , H01L2224/05578 , H01L2224/05644 , H01L2224/05655 , H01L2224/10165 , H01L2224/1147 , H01L2224/13028 , H01L2224/13099 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75252 , H01L2224/75743 , H01L2224/8113 , H01L2224/81132 , H01L2224/81136 , H01L2224/81801 , H01L2224/83136 , H01L2224/83856 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01043 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34 on at least one of first and second bases 10A and 40 to be bonded together at their corresponding electrodes (e.g., electrodes 15 and electrodes 41); aligning the electrodes 15 of the first base 10A to positions corresponding to the electrodes 41 of the second base 40 for connection, by means of magnetic forces of the magnetic bumps 34 formed over the first base 10A; and connecting the electrodes 15 of the first base 10A to the electrodes 41 of the second base 40, wherein the alignment is made for a plurality of the first bases 10A at a time.
摘要翻译：为了提供一种用于在短时间内将一对基极（例如，一对半导体芯片和电路板或一对半导体芯片）的电极连接在一起的低成本，高效的半导体器件制造方法。本发明的方法包括：在第一和第二基底10A和40中的至少一个上形成磁性凸块34，以在其相应的电极（例如电极15和电极41）处接合在一起; 通过形成在第一基座10A上的磁性凸块34的磁力将第一基座10A的电极15对准到与第二基座40的电极41相对应的连接位置; 并且将第一基座10A的电极15连接到第二基座40的电极41，其中一次对多个第一基座10A进行对准。

10. 发明申请

US20070231961A1 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20070231961A1
公开(公告)日：2007-10-04
申请号：US11515994
申请日：2006-09-06
申请人： Kazuo Teshirogi , Yuzo Shimobeppu , Kazuhiro Yoshimoto , Yoshiaki Shinjo , Masataka Mizukoshi
发明人： Kazuo Teshirogi , Yuzo Shimobeppu , Kazuhiro Yoshimoto , Yoshiaki Shinjo , Masataka Mizukoshi
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/563 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/544 , H01L24/11 , H01L24/12 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/90 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2221/68322 , H01L2221/68336 , H01L2221/68354 , H01L2223/54426 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05572 , H01L2224/05578 , H01L2224/05644 , H01L2224/05655 , H01L2224/10165 , H01L2224/1147 , H01L2224/13028 , H01L2224/13099 , H01L2224/1329 , H01L2224/133 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75252 , H01L2224/75743 , H01L2224/8113 , H01L2224/81132 , H01L2224/81136 , H01L2224/81801 , H01L2224/83136 , H01L2224/83856 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01043 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34 on at least one of first and second bases 10A and 40 to be bonded together at their corresponding electrodes (e.g., electrodes 15 and electrodes 41); aligning the electrodes 15 of the first base 10A to positions corresponding to the electrodes 41 of the second base 40 for connection, by means of magnetic forces of the magnetic bumps 34 formed over the first base 10A; and connecting the electrodes 15 of the first base 10A to the electrodes 41 of the second base 40, wherein the alignment is made for a plurality of the first bases 10A at a time.
摘要翻译：为了提供一种用于在短时间内将一对基极（例如，一对半导体芯片和电路板或一对半导体芯片）的电极连接在一起的低成本，高效的半导体器件制造方法。本发明的方法包括：在第一和第二基底10A和40中的至少一个上形成磁性凸块34，以在其相应的电极（例如电极15和电极41）处接合在一起; 通过形成在第一基座10A上的磁性凸块34的磁力将第一基座10A的电极15对准到与第二基座40的电极41相对应的连接位置; 并且将第一基座10A的电极15连接到第二基座40的电极41，其中一次对多个第一基座10A进行对准。

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