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1. 发明授权

US4815040A Static memory using a MIS field effect transistor 失效
标题翻译：使用MIS场效应晶体管的静态存储器
公开(公告)号：US4815040A
公开(公告)日：1989-03-21
申请号：US100640
申请日：1987-09-24
申请人： Masataka Matsui , Takayuki Ohtani
发明人： Masataka Matsui , Takayuki Ohtani
IPC分类号： G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.
摘要翻译：在选定的列中，不选择上拉晶体管对，而是选择传输栅极晶体管对。在读取模式下，传输栅极晶体管对用作位线对之间的上拉负载。然而，传输栅极晶体管对保持截止，直到位线对上的电压从电源电位电平降低到传输栅极晶体管的阈值电压电平。因此，当位线对上的电压在等于电源电位电平的电压到低于电源电位的电位的范围内时，在位线对中不形成直流电流路径，阈值电压电平，并且位线对上的电位差的增加速率由存储单元的引入电流决定。因此，可以实现高速感测操作。在写入模式下，传输栅极晶体管对用于位线上拉功能。由于没有布置正常导通的位线负载晶体管，所以不存在包括位线对的直流电路，因此可以实现低功耗。

2. 发明授权

US4813022A Static memory with pull-up circuit for pulling-up a potential on a bit line 失效
标题翻译：具有上拉电路的静态存储器，用于提升位线上的电位
公开(公告)号：US4813022A
公开(公告)日：1989-03-14
申请号：US136769
申请日：1987-12-22
申请人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
发明人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00 , G11C11/34
CPC分类号： G11C7/12 , G11C11/419
摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
摘要翻译：位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。可以高速地增加一对位线之间的电压差，从而增加读出速度。

3. 发明授权

US4881202A Semiconductor memory device using partial decoders for redundancy 失效
标题翻译：半导体存储器件使用部分解码器进行冗余
公开(公告)号：US4881202A
公开(公告)日：1989-11-14
申请号：US138800
申请日：1987-12-29
申请人： Jun-ichi Tsujimoto , Masataka Matsui , Hiroshi Iwai , Takayuki Ohtani
发明人： Jun-ichi Tsujimoto , Masataka Matsui , Hiroshi Iwai , Takayuki Ohtani
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04
CPC分类号： G11C29/802 , G11C29/844
摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.

4. 发明授权

US09074575B2 Energization control apparatus for glow plug 有权
标题翻译：电热塞电能控制装置
公开(公告)号：US09074575B2
公开(公告)日：2015-07-07
申请号：US13157760
申请日：2011-06-10
申请人： Takayuki Sakurai , Takayuki Ohtani
发明人： Takayuki Sakurai , Takayuki Ohtani
IPC分类号： F23Q7/00 , F23Q13/00 , F02P19/02 , F02D41/24
CPC分类号： F02P19/025 , F02D41/2432 , F02D41/2464 , F02P19/027
摘要： A GCU (21) includes calibration means (33) which supplies electric current to a glow plug (1) when an internal combustion engine EN to which the glow plug (1) is attached is stopped, to thereby obtain a pre-correction target resistance of the glow plug (1). The calibration means (33) supplies a predetermined first electric power to the glow plug (1) in a predetermined first energization period, and supplies a predetermined second electric power to the glow plug (1) after the first energization period. The second electric power is set such that, when the second electric power is supplied to the glow plug (1) and the temperature of the glow plug (1) becomes saturated, the temperature of the glow plug (1) becomes equal to the target temperature. Further, the first electric power is greater than the second electric power.
摘要翻译： GCU（21）包括当安装了电热塞（1）的内燃机EN停止时向电热塞（1）供应电流的校准装置（33），从而获得预校正目标电阻的电热塞（1）。校准装置（33）在预定的第一通电时段内向预热塞（1）提供预定的第一电力，并且在第一通电时段之后向预热塞（1）提供预定的第二电力。第二电力被设定为使得当第二电力被提供给电热塞（1）并且电热塞（1）的温度饱和时，电热塞（1）的温度变得等于目标温度。此外，第一电力大于第二电力。

5. 发明授权

US08423197B2 Apparatus for controlling the energizing of a heater 有权
标题翻译：用于控制加热器通电的装置
公开(公告)号：US08423197B2
公开(公告)日：2013-04-16
申请号：US12623812
申请日：2009-11-23
申请人： Takayuki Sakurai , Takayuki Ohtani , Hiroki Tsuchiya
发明人： Takayuki Sakurai , Takayuki Ohtani , Hiroki Tsuchiya
IPC分类号： G05D23/19
CPC分类号： F02P19/025 , F02D41/042 , F02D41/2464 , F02P19/027
摘要： A heater energization control apparatus. When an engine is stopped, a microcomputer of a GCU enters a power save mode. When the microcomputer returns to a normal mode in response to an interruption signal periodically generated from an interruption timer, the microcomputer supplies electricity to a heating resistor for a short time and obtains its resistance (S19). When the resistance is greater than a first reference value, the microcomputer determines that a glow plug is removed from the engine; that is, the glow plug is being exchanged (S29). The microcomputer sets an exchange flag to “1” (S30), and performs calibration for the heating resistor of a new glow plug after the engine is operated next time (S35). When the current resistance becomes smaller than the past resistance, the microcomputer determines that the glow plug has been exchanged.
摘要翻译：一种加热器通电控制装置。当发动机停止时，GCU的微型计算机进入省电模式。当微计算机响应于从中断定时器周期性地产生的中断信号而返回到正常模式时，微计算机在短时间内向加热电阻器供电并获得其电阻（S19）。当电阻大于第一参考值时，微型计算机确定从发动机移除电热塞; 也就是说，正在更换电热塞（S29）。微型计算机将交换标志设置为1（S30），并且在发动机下一次操作之后对新的电热塞的加热电阻器进行校准（S35）。当电流电阻变得小于过去电阻时，微机确定电热塞已被更换。

6. 发明授权

US4697112A Current-mirror type sense amplifier 失效
标题翻译：电流镜式读出放大器
公开(公告)号：US4697112A
公开(公告)日：1987-09-29
申请号：US878372
申请日：1986-06-25
申请人： Takayuki Ohtani , Mitsuo Isobe , Akira Aono , Nobuaki Urakawa
发明人： Takayuki Ohtani , Mitsuo Isobe , Akira Aono , Nobuaki Urakawa
IPC分类号： H03K5/02 , G11C11/409 , G11C11/419 , H03F3/45 , H03K3/356
CPC分类号： H03F3/45183 , H03K3/356104 , H03F2203/45394 , H03F2203/45466 , H03F2203/45644 , H03F2203/45674 , H03F2203/45726
摘要： There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.
摘要翻译：公开了一种感测放大器，其特征在于包括一个上拉电路。上拉电路包括布置在一对输出节点之间的第一个和上拉电源电势节点之间的第一晶体管，以及布置在该对输出节点中的第二个和上拉电源之间的第二晶体管潜在节点。第一晶体管的栅极连接到第二输出节点，第二晶体管的栅极连接到第一输出节点。

7. 发明授权

US08847118B2 Energization control apparatus for glow plug 有权
标题翻译：电热塞电能控制装置
公开(公告)号：US08847118B2
公开(公告)日：2014-09-30
申请号：US13157839
申请日：2011-06-10
申请人： Takayuki Sakurai , Takayuki Ohtani
发明人： Takayuki Sakurai , Takayuki Ohtani
IPC分类号： F23Q7/00 , F23Q13/00 , F02P19/02
CPC分类号： F02P19/025 , F02P19/026 , F02P19/027
摘要： An energization control apparatus for a glow plug (21) includes temperature maintaining energization means (34), and intermediate temperature raising means 35 for resuming energization of the glow plug 1 during operation of an engine EN after energization by the temperature maintaining energization means (34). The intermediate temperature raising means (35) includes resistance acquisition means (32); difference calculation means (36) for calculating a difference between the resistance of the glow plug (1) and a target resistance; intermediate value setting means (37); and intermediate value update means (38) for gradually increasing an intermediate target resistance such that the intermediate target resistance finally coincides with the target resistance. The voltage applied to the glow plug (1) is controlled such that the resistance of the glow plug (1) coincides with the intermediate target resistance.
摘要翻译：一种用于电热塞（21）的通电控制装置包括温度保持通电装置（34）和用于在由保温通电装置（34）通电之后在发动机EN运行期间恢复电热塞1的通电的中间温度升高装置35 ）。中间升温装置（35）包括电阻获取装置（32）; 差分计算装置（36），用于计算电热塞（1）的电阻与目标电阻之间的差; 中间值设定装置（37）; 以及用于逐渐增加中间目标电阻使得中间目标电阻最终与目标电阻一致的中间值更新装置（38）。控制施加到电热塞（1）的电压使得电热塞（1）的电阻与中间目标电阻重合。

8. 发明授权

US06502251B1 Water closet and flushing water feed device 失效
标题翻译：水箱和冲水给水装置
公开(公告)号：US06502251B1
公开(公告)日：2003-01-07
申请号：US09830867
申请日：2001-04-30
申请人： Kunihiko Teshima , Tatsuhiro Kosugi , Taiji Sugita , Takayuki Ohtani , Kenichi Nagato , Yoshitaka Suehiro
发明人： Kunihiko Teshima , Tatsuhiro Kosugi , Taiji Sugita , Takayuki Ohtani , Kenichi Nagato , Yoshitaka Suehiro
IPC分类号： E03D100
CPC分类号： E03D5/01 , E03D1/36
摘要： A flush toilet 1 has a toilet flushing tank device 7 for discharging flushing water to a toilet bowl 2. This tank device is built into a tank storage region 5 to the rear of the toilet bowl 2, and comprises a flushing water tank 8 and a jet pump 13 disposed submerged in this flushing water tank 8. Flushing water (operating water) is supplied to this jet pump 13 via a flush valve 11 and a pipe 12 downstream from this valve. The jet pump 13 comprises a spray nozzle 131 and a throat 132 opposite thereto. Because the jet pump 13 is connected directly to a pipe 14, all of the flushing water jetted from the jet pump 13 passes directly to the pipe 14, and is guided by this pipe 14 to a rim water channel 4b.
摘要翻译：冲水马桶1具有用于将冲洗水排放到马桶2的马桶冲洗罐装置7.该罐装置被装入到马桶2的后部的储罐区域5中，并且包括冲洗水箱8和喷射泵13设置在浸没在该冲洗水槽8中的冲洗水中。冲洗水（操作水）经由冲洗阀11和该阀下游的管道12供给该喷射泵13。喷射泵13包括喷嘴131和与其相对的喉部132。由于喷射泵13直接与管道14连接，所以从喷射泵13喷射的所有冲洗水直接通过管道14，并被该管道14引导到边缘水通道4b。

9. 发明授权

US4982365A Semiconductor memory device with a potential level-setting circuit 失效
标题翻译：具有电位电平设定电路的半导体存储器件
公开(公告)号：US4982365A
公开(公告)日：1991-01-01
申请号：US476137
申请日：1990-02-07
申请人： Takayuki Ohtani , Mitsuo Isobe
发明人： Takayuki Ohtani , Mitsuo Isobe
IPC分类号： G11C11/41 , G11C7/20 , G11C11/401 , G11C11/419
CPC分类号： G11C7/20 , G11C11/419
摘要： During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.
摘要翻译：在数据清除操作期间，在保持关断状态下，与至少一列相关联的每个静态型存储单元中的传输栅极晶体管，并入存储单元中的两个驱动晶体管中的一个的源极被设置为高电位电平，另一个驱动晶体管的源极为低电平。结果，在存储单元矩阵中执行清零操作至少为1列。由于存储器件的布置，在清除操作期间不需要地址选择操作来选择存储器单元。此外，清除操作以存储单元矩阵中的1列的最小单位进行。因此，清除操作的处理时间减少。此外，由于在清除动作期间存储单元中的传输栅极晶体管保持在截止状态，所以清除操作期间流过的直流电流减小，结果是功耗降低。

10. 发明授权

US4760562A MOS static memory circuit 失效
标题翻译： MOS静态存储电路
公开(公告)号：US4760562A
公开(公告)日：1988-07-26
申请号：US800270
申请日：1985-11-21
申请人： Takayuki Ohtani
发明人： Takayuki Ohtani
IPC分类号： G11C11/419 , G11C13/00 , G11C7/00
CPC分类号： G11C11/419
摘要： Voltage converters are arranged in units of columns in a memory device. Each voltage converter is connected to a column decoder. The column decoder receives a column address signal and supplies a column selection signal to the voltage converter. The voltage converters apply a ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the selected columns, and a voltage higher than the ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the nonselected columns so as to decrease power consumption in the nonselected columns as compared with that in the selected columns.
摘要翻译：电压转换器以存储器件中的列为单位排列。每个电压转换器连接到列解码器。列解码器接收列地址信号，并将电压转换器提供列选择信号。电压转换器对所选择的列的存储器单元的驱动晶体管对的源极结施加接地电平，并且将高于对于等级电压的接地电平的电压施加到所述存储器单元的驱动晶体管对的源极结非选择列，以便与所选列相比减少非选择列中的功耗。

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