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1. 发明授权

US4881202A Semiconductor memory device using partial decoders for redundancy 失效
标题翻译：半导体存储器件使用部分解码器进行冗余
公开(公告)号：US4881202A
公开(公告)日：1989-11-14
申请号：US138800
申请日：1987-12-29
申请人： Jun-ichi Tsujimoto , Masataka Matsui , Hiroshi Iwai , Takayuki Ohtani
发明人： Jun-ichi Tsujimoto , Masataka Matsui , Hiroshi Iwai , Takayuki Ohtani
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04
CPC分类号： G11C29/802 , G11C29/844
摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.

2. 发明授权

US4813022A Static memory with pull-up circuit for pulling-up a potential on a bit line 失效
标题翻译：具有上拉电路的静态存储器，用于提升位线上的电位
公开(公告)号：US4813022A
公开(公告)日：1989-03-14
申请号：US136769
申请日：1987-12-22
申请人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
发明人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00 , G11C11/34
CPC分类号： G11C7/12 , G11C11/419
摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
摘要翻译：位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。可以高速地增加一对位线之间的电压差，从而增加读出速度。

3. 发明授权

US4931994A Static semiconductor memory with section and block sense amplifiers 失效
标题翻译：具有截面和块读出放大器的静态半导体存储器
公开(公告)号：US4931994A
公开(公告)日：1990-06-05
申请号：US156537
申请日：1988-02-16
申请人： Masataka Matsui , Jun-ichi Tsujimoto , Takayuki Ootani , Mitsuo Isobe
发明人： Masataka Matsui , Jun-ichi Tsujimoto , Takayuki Ootani , Mitsuo Isobe
IPC分类号： G11C11/41 , G11C11/401 , G11C11/409 , G11C11/419
CPC分类号： G11C11/419
摘要： A static semiconductor memory comprises a word line, a memory cell array divided into a plurality of blocks in an extending direction of the word line, each block including a plurality of sections each of which includes a plurality of static memory cells, a controller, a section data line provided for each section, first sense amplifiers, a block data line provided for each block, second sense amplifiers, a main data line and a latch circuit for latching data on the main data line. The controller selects an arbitrary section in the memory cell array at the time of data readout and controls the reading of data from memory cells included in the selected section. The section data line is supplied with data read out from the memory cells. The first sense amplifiers, coupled at their input terminals to the section data line, are activated only when their associated section is selected. The individual first sense amplifiers in the same block have their output terminals commonly coupled to the block data line. Each second sense amplifier, coupled at its input terminal to the associated block data line, is activated only when the sections belonging to that block are selected. The second sense amplifiers have their output terminals commonly coupled to the main data line.
摘要翻译：静态半导体存储器包括字线，在字线的延伸方向上划分成多个块的存储单元阵列，每个块包括多个部分，每个部分包括多个静态存储器单元，控制器，为每个部分提供的部分数据线，第一读出放大器，为每个块提供的块数据线，第二读出放大器，主数据线和用于锁存主数据线上的数据的锁存电路。控制器在数据读出时选择存储单元阵列中的任意部分，并且控制从所选部分中包括的存储单元读取数据。区段数据线被提供有从存储单元读出的数据。在其输入端子耦合到区段数据线的第一读出放大器仅在选择相关区段时被激活。同一块中的各个第一读出放大器的输出端通常耦合到块数据线。每个第二读出放大器在其输入端耦合到相关联的块数据线，仅在属于该块的部分被选择时被激活。第二读出放大器的输出端通常耦合到主数据线。

4. 发明授权

US4694427A Programmable semiconductor memory device with combined sense amplification and programming capability 失效
标题翻译：具有组合感测放大和编程能力的可编程半导体存储器件
公开(公告)号：US4694427A
公开(公告)日：1987-09-15
申请号：US759433
申请日：1985-07-26
申请人： Junichi Miyamoto , Jun-ichi Tsujimoto
发明人： Junichi Miyamoto , Jun-ichi Tsujimoto
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/28 , G11C11/40
CPC分类号： G11C16/28
摘要： A semiconductor memory device provided with first and second bit lines, each of which is connected to a memory cell comprising a nonvolatile transistor and a dummy cell comprising a nonvolatile transistor. The first and second bit lines are respectively connected to high voltage generators which are applied at the time of data programming. At the time of data reading, data-detecting and storing means comprising a flip-flop circuit detects data, while amplifying a potential difference between the first and second bit lines. At the time of data writing, the data detecting and storing means temporarily stores data in accordance with the contents of externally supplied writing data. A first switching transistor is provided between the first data input-output node of the data-detecting and storing means and the first bit line. The second switching transistor is connected between the second data input-output node of the data-detecting and storing means and second bit line. The paired switching transistors are controlled in accordance with the operation mode of the memory device.
摘要翻译：一种具有第一和第二位线的半导体存储器件，每个位线连接到包括非易失性晶体管的存储单元和包括非易失性晶体管的虚设单元。第一和第二位线分别连接到在数据编程时应用的高电压发生器。在数据读取时，包括触发器电路的数据检测和存储装置在放大第一和第二位线之间的电位差的同时检测数据。在数据写入时，数据检测和存储装置根据外部提供的写入数据的内容临时存储数据。第一开关晶体管设置在数据检测和存储装置的第一数据输入 - 输出节点与第一位线之间。第二开关晶体管连接在数据检测和存储装置的第二数据输入输出节点和第二位线之间。成对的开关晶体管根据存储器件的操作模式进行控制。

5. 发明授权

US4868483A Power voltage regulator circuit 失效
标题翻译：电源稳压电路
公开(公告)号：US4868483A
公开(公告)日：1989-09-19
申请号：US55548
申请日：1987-05-29
申请人： Jun-ichi Tsujimoto
发明人： Jun-ichi Tsujimoto
IPC分类号： G05F3/24 , G05F1/46 , G11C11/407 , H01L21/8234 , H01L27/04 , H01L27/06 , H03F3/34 , H03F3/343
CPC分类号： G05F1/465
摘要： A power voltage regulator circuit has a power terminal to which an external power voltage is supplied, an output line, and a voltage-drop circuit connected between the power terminal and the output line. The voltage drop circuit includes an N-channel MOS transistor having a drain connected to the power terminal and a source connected to the output line, a constant voltage generator for supplying a voltage, lower than the external power voltage, to a gate of the MOS transistor, and a semiconductor well whose surface area serves as a channel region of the MOS transistor.

6. 发明授权

US5990706A Logic circuit and method of designing the same 失效
标题翻译：逻辑电路及其设计方法
公开(公告)号：US5990706A
公开(公告)日：1999-11-23
申请号：US827506
申请日：1997-03-28
申请人： Nobu Matsumoto , Kimiyoshi Usami , Jun-ichi Tsujimoto
发明人： Nobu Matsumoto , Kimiyoshi Usami , Jun-ichi Tsujimoto
IPC分类号： H03K19/00 , G06F17/50 , H03K19/096
CPC分类号： H03K19/0963
摘要： A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).
摘要翻译： CMOS逻辑电路由用作逻辑门1的多米诺骨门组成，不配置在关键路径上并在较低电源电压（VDDL）上运行，另一个多米诺骨门用作在较高电源电压（VDDH）上工作的逻辑门2，。逻辑门1的输出是逻辑门2的输入。在逻辑门1和2之间没有配置电平转换器，因此CMOS逻辑电路的功耗很小。 CMOS逻辑电路根据满足定时要求并最大化在较低电源电压（VDDL）上工作的逻辑门数量的方法进行设计。

7. 发明授权

US4728829A Timer circuit 失效
标题翻译：定时器电路
公开(公告)号：US4728829A
公开(公告)日：1988-03-01
申请号：US724417
申请日：1985-04-18
申请人： Jun-ichi Tsujimoto
发明人： Jun-ichi Tsujimoto
IPC分类号： H03K17/28 , G11C7/22 , H03K17/296 , H03K17/687
CPC分类号： G11C7/22
摘要： A timer circuit which is used for write and erase time control of a semicondcutor memory, and configured so as to transfer a charge of a charge storage capacitor to a charge pump capacitor through a first transfer gate thereafter to repeatedly effect a discharge operation by using a second transfer gate thereby to gradually reduce a charge of the charge storage capacitor, thus performing a timer operation, characterized in that there is provided a circuit for making an adjustment such that a voltage applied to the charge pump capacitor is smaller than a voltage applied to the charge storage capacitor.
摘要翻译：一种定时器电路，用于半切割器存储器的写入和擦除时间控制，并经配置以便经过第一传输门将电荷存储电容器的电荷转移到电荷泵电容器之后，通过使用第二传输门，从而逐渐减小电荷存储电容器的电荷，从而执行定时器操作，其特征在于提供一个电路，用于进行调节，使得施加到电荷泵电容器的电压小于施加到电荷存储电容器。

8. 发明授权

US4935644A Charge pump circuit having a boosted output signal 失效
标题翻译：电荷泵电路具有升压的输出信号
公开(公告)号：US4935644A
公开(公告)日：1990-06-19
申请号：US228156
申请日：1988-08-04
申请人： Jun-ichi Tsujimoto
发明人： Jun-ichi Tsujimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H02M3/073
摘要： A semiconductor integrated circuit device is provided which comprises a first charge pumping circuit comprising a plurality of MOS transistors cascade-connected between an input voltage node and a booster output node, where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor, a second charge pumping circuit comprising a plurality of MOS transistors cascade-connected between the input voltage node and the booster output node and equal in number to those of the first charge pumping circuit where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor and the gates of the respective MOS transistors are connected to the gate of the corresponding MOS transistors, and a high resistive element connected to an output terminal of said first charge pumping circuit.

9. 发明授权

US4680735A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4680735A
公开(公告)日：1987-07-14
申请号：US759142
申请日：1985-07-26
申请人： Junichi Miyamoto , Jun-ichi Tsujimoto
发明人： Junichi Miyamoto , Jun-ichi Tsujimoto
IPC分类号： G11C17/18 , G11C5/06 , G11C5/14 , G11C7/06 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/419 , G11C16/06 , G11C17/00 , G11C7/02
CPC分类号： G11C8/14 , G11C5/063 , G11C5/14 , G11C7/065
摘要： A sense amplifier comprising a flip-flop circuit is provided for each bit line pair. A first transistor is connected between the flip-flop circuit and V.sub.DD power source. A second transistor is connected between the flip-flop circuit and ground. A control signal for controlling the active state of the flip-flop is applied to the gate of the first transistor, with a minimum time delay. The control signal is also applied to the gate of the second transistor, with a time delay corresponding to that caused by the word line. The timing for rendering each flip-flop circuit in the active state is substantially coincident with the optimum timing of a change in potential on each corresponding bit line.
摘要翻译：为每个位线对提供包括触发器电路的读出放大器。第一晶体管连接在触发器电路和VDD电源之间。第二晶体管连接在触发器电路和地之间。用于控制触发器的有效状态的控制信号以最小的时间延迟施加到第一晶体管的栅极。控制信号也被施加到第二晶体管的栅极，时间延迟对应于由字线引起的时间延迟。使每个触发器电路处于活动状态的定时基本上与每个相应位线上的电位变化的最佳定时一致。

10. 发明授权

US4679196A Semiconductor memory device with a bit error detecting function 失效
标题翻译：具有位错检测功能的半导体存储器件
公开(公告)号：US4679196A
公开(公告)日：1987-07-07
申请号：US705788
申请日：1985-02-26
申请人： Jun-ichi Tsujimoto
发明人： Jun-ichi Tsujimoto
IPC分类号： G06F12/16 , G06F11/10 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076
摘要： A memory matrix array consists of a plurality of memory cells with addresses expressed by a plurality of bits. The parity bit for the data stored in all of the memory cells of each linear memory cell array in the row direction are stored in the corresponding one of a plurality of parity storage cells. Storage is made into second and third parity storage cells, respectively, the parity bits for the data stored in all of the memory cells which are specified such that the corresponding bits of the addresses of the memory cells in the memory matrix array are high in logical level. In a read mode, the parity is read out from the first to third parity storage cells of the parity memory circuit.
摘要翻译：存储矩阵阵列由多个具有由多个位表示的地址的存储单元组成。存储在行方向上的每个线性存储单元阵列的所有存储单元中的数据的奇偶校验位被存储在多个奇偶校验存储单元中的对应的一个奇偶校验存储单元中。存储分别被制成第二和第三奇偶校验存储单元，存储在所有存储单元中的数据的奇偶校验位被指定为使得存储器矩阵阵列中的存储单元的地址的对应位为逻辑高水平。在读取模式中，从奇偶校验存储器电路的第一至第三奇偶校验存储单元中读出奇偶校验。

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