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1. 发明授权

US06606688B1 Cache control method and cache controller 失效
标题翻译：缓存控制方法和缓存控制器
公开(公告)号：US06606688B1
公开(公告)日：2003-08-12
申请号：US09642002
申请日：2000-08-21
申请人： Masaru Koyanagi , Disuke Yamane , Hideya Akashi , Yuji Tsushima , Tadayuki Sakakibara
发明人： Masaru Koyanagi , Disuke Yamane , Hideya Akashi , Yuji Tsushima , Tadayuki Sakakibara
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.
摘要翻译：缓存控制器存储用于预取块大小和步幅值的预设变量。缓存控制器从处理器接收对主存储器的访问请求，并且基于访问请求和变量生成预取请求。高速缓存控制器基于生成的预取请求从主存储器读取数据，并将该数据写入缓存存储器。

2. 发明授权

US06993633B1 Computer system utilizing speculative read requests to cache memory 失效
标题翻译：计算机系统利用推测读请求来缓存内存
公开(公告)号：US06993633B1
公开(公告)日：2006-01-31
申请号：US09628718
申请日：2000-07-28
申请人： Tadayuki Sakakibara , Isao Ohara , Hideya Akashi , Yuji Tsushima , Satoshi Muraoka
发明人： Tadayuki Sakakibara , Isao Ohara , Hideya Akashi , Yuji Tsushima , Satoshi Muraoka
IPC分类号： G06F9/38
CPC分类号： G06F12/0862 , G06F12/084
摘要： A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.
摘要翻译：一种用于计算机系统的高速缓存数据控制系统和方法，其中在存储器读取处理中，相干控制器在读取之前向高速缓存数据控制器发送用于（推测性地）将数据从高速缓存数据部分读取的高级推测性读请求缓存标签从缓存标签部分进行缓存命中检查。如果发生了高速缓存命中，则高速缓存数据控制器接收到由相干控制器发出的读请求时，将经过推测读取的数据作为响应数据返回。

3. 发明授权

US5617575A Interprocessor priority control system for multivector processor 失效
标题翻译：多处理器处理器优先级控制系统
公开(公告)号：US5617575A
公开(公告)日：1997-04-01
申请号：US170743
申请日：1993-12-21
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F12/00 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

4. 发明授权

US5590353A Vector processor adopting a memory skewing scheme for preventing degradation of access performance 失效
标题翻译：矢量处理器采用存储器偏移方案来防止访问性能下降
公开(公告)号：US5590353A
公开(公告)日：1996-12-31
申请号：US275388
申请日：1994-07-15
申请人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
发明人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
IPC分类号： G06F9/345 , G06F9/38 , G06F12/00 , G06F12/06 , G06F15/78 , G06F17/16 , G06F15/16
CPC分类号： G06F15/8061 , G06F9/345 , G06F9/3455 , G06F9/3824
摘要： A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.
摘要翻译：矢量处理器包括存储控制装置，该存储控制装置包括具有地址解码单元的访问请求缓冲单元，地址解码单元具有与属于同一机器系列的所有向量处理器模型对应的地址解码器电路。通过使用模型ID信号，地址解码由选择器选择性地启用。地址解码单元对属于同一机器系列的处理器的所有元素并行因子对存储器模块的地址分配进行偏移或偏移的周期性进行均衡。提供访问请求队列优先于包含在存储控制装置中的访问请求优先级确定单元的必要数量级。

5. 发明授权

US5339429A Parallel processing system and compiling method used therefor 失效
标题翻译：并行处理系统及其编译方法
公开(公告)号：US5339429A
公开(公告)日：1994-08-16
申请号：US880544
申请日：1992-05-08
申请人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
发明人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
IPC分类号： G06F9/45 , G06F12/02 , G06F15/167 , G06F9/44 , G06F12/12
CPC分类号： G06F8/44 , G06F12/0284 , G06F15/167
摘要： A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage device. The tightly coupled multiprocessors are connected with each other through a shared extended storage device. A compiler or preprocessor for the system analyzes the data to be allocated on the extended storage devices so that large scaled data accessed from each tightly-coupled multiprocessor are allocated on the local extended storage whereas the data to be accessed from a plurality of tightly-coupled multiprocessors are allocated on the shared extended storage.
摘要翻译：并行处理系统包括紧密耦合的多处理器。每个多处理器都包含一个本地扩展存储设备，它是主存储设备的辅助存储设备。紧密耦合的多处理器通过共享扩展存储设备彼此连接。用于系统的编译器或预处理器分析在扩展存储设备上要分配的数据，使得从每个紧密耦合的多处理器访问的大规模数据被分配在本地扩展存储器上，而从多个紧耦合多处理器分配在共享扩展存储上。

6. 发明申请

US20050166089A1 Method for processing a diagnosis of a processor, information processing system and a diagnostic processing program 失效
标题翻译：用于处理处理器，信息处理系统和诊断处理程序的诊断的方法
公开(公告)号：US20050166089A1
公开(公告)日：2005-07-28
申请号：US11017942
申请日：2004-12-22
申请人： Masanao Ito , Tadayuki Sakakibara
发明人： Masanao Ito , Tadayuki Sakakibara
IPC分类号： G06F15/177 , G06F9/46 , G06F11/00 , G06F11/22
CPC分类号： G06F11/079 , G06F11/0724 , G06F11/3466
摘要： In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.
摘要翻译：在包括一个或多个处理器的信息处理系统中，以预定频率执行诊断程序以诊断处理器。诊断程序以预定的频率，以预定的时间间隔生成一个或多个处理或线程，例如诊断处理器。生成的进程或线程在每个处理器上执行诊断，并且在处理器中检测到故障的进程或线程通过将故障信息存储在存储器中来完成其执行。除了故障处理器之外的另一个处理器的进程或线程是指有关故障处理器的故障信息，并执行故障排除过程。

7. 发明授权

US5530881A Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs 失效
标题翻译：用于处理与混合型程序和单独类型程序相对应的不同指令集架构的矢量处理装置
公开(公告)号：US5530881A
公开(公告)日：1996-06-25
申请号：US894633
申请日：1992-06-05
申请人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
发明人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
IPC分类号： G06F9/318 , G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F9/30189 , G06F15/8076 , G06F9/30036 , G06F9/3877
摘要： A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.
摘要翻译：用于处理从存储器取出的向量指令和缩放器指令的向量处理器系统包括存储器存储器，连接到存储器存储器的第一和第二定标器处理单元，连接到存储器存储器和两个定标器处理单元的矢量处理单元，以及用于在缩放器指令/向量指令混合类型程序的处理期间处理在缩放器指令/向量指令单独类型程序和从第二缩放器处理单元接收的向量指令的处理期间处理从存储器存储器获取的向量指令。更具体地说，对于缩放器指令/向量指令混合型程序，向量处理单元从缩放器处理单元接收向量指令，而对于缩放器指令/向量指令单独类型程序，向量处理单元直接从存储器检索向量指令存储。

8. 发明授权

US07421618B2 Method for processing a diagnosis of a processor, information processing system and a diagnostic processing program 失效
标题翻译：用于处理处理器，信息处理系统和诊断处理程序的诊断的方法
公开(公告)号：US07421618B2
公开(公告)日：2008-09-02
申请号：US11017942
申请日：2004-12-22
申请人： Masanao Ito , Tadayuki Sakakibara
发明人： Masanao Ito , Tadayuki Sakakibara
IPC分类号： G06F11/00
CPC分类号： G06F11/079 , G06F11/0724 , G06F11/3466
摘要： In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.
摘要翻译：在包括一个或多个处理器的信息处理系统中，以预定频率执行诊断程序以诊断处理器。诊断程序以预定的频率，以预定的时间间隔生成一个或多个处理或线程，例如诊断处理器。生成的进程或线程在每个处理器上执行诊断，并且在处理器中检测到故障的进程或线程通过将故障信息存储在存储器中来完成其执行。除了故障处理器之外的另一个处理器的进程或线程是指有关故障处理器的故障信息，并执行故障排除过程。

9. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

10. 发明授权

US5809539A Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs 失效
标题翻译：具有地址分配和地址锁定能力的处理器系统适用于由同步DRAM组成的存储器
公开(公告)号：US5809539A
公开(公告)日：1998-09-15
申请号：US637283
申请日：1996-04-24
申请人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki
IPC分类号： G06F12/06 , G06F13/16 , G06F12/00
CPC分类号： G06F13/1631 , G06F12/0607
摘要： In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.
摘要翻译：为了利用包括同步DRAM等的多个存储器组的行地址锁定操作模式并且被划分为多个真实存储体组，例如，比存储器组多于多个每个跨越真实银行集团的逻辑组。以块交织的方式，以每个逻辑组为单位分配地址。当由给定请求者发出的一系列请求包括访问同一存储体中相同行地址的多个请求时，该请求者请求该行地址被锁定以供多个请求访问。锁请求由行地址管理单元保留。当来自另一请求者的后续请求请求访问除同一存储体中的锁定地址之外的行地址时，优先级电路优先选择已经锁定存储器的初始请求者的预定数量的请求，优先于另一请求请求者

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