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1. 发明申请

US20050170587A1 Power MOSFET semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20050170587A1
公开(公告)日：2005-08-04
申请号：US11060357
申请日：2005-02-18
申请人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
发明人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L29/15
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/66712
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.

2. 发明授权

US06878989B2 Power MOSFET semiconductor device and method of manufacturing the same 失效
标题翻译：功率MOSFET半导体器件及其制造方法
公开(公告)号：US06878989B2
公开(公告)日：2005-04-12
申请号：US10151900
申请日：2002-05-22
申请人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
发明人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L29/732
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/66712
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，其上形成有沿深度方向朝向半导体衬底延伸的沟槽的半导体层。第一导电类型的第一区域沿着半导体层中的沟槽的一侧在深度方向上形成并接触半导体衬底。第一导电类型的第二区域形成在半导体层的表面区域中并且靠近沟槽并与第一区域接触。第二导电类型的第三区域形成在半导体层的表面区域中。第一导电类型的第四区域形成在第三区域的表面区域中。栅极绝缘膜和栅电极设置在第二区域和第四区域之间的第三区域的表面上。

3. 发明授权

US07226841B2 Power MOSFET semiconductor device and method of manufacturing the same 失效
标题翻译：功率MOSFET半导体器件及其制造方法
公开(公告)号：US07226841B2
公开(公告)日：2007-06-05
申请号：US11060357
申请日：2005-02-18
申请人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
发明人： Masaru Izumisawa , Shigeo Kouzuki , Shinichi Hodama
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/66712
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，其上形成有沿深度方向朝向半导体衬底延伸的沟槽的半导体层。第一导电类型的第一区域沿着半导体层中的沟槽的一侧的深度方向形成并接触半导体衬底。第一导电类型的第二区域形成在半导体层的表面区域中并且靠近沟槽并与第一区域接触。第二导电类型的第三区域形成在半导体层的表面区域中。第一导电类型的第四区域形成在第三区域的表面区域中。栅极绝缘膜和栅电极设置在第二区域和第四区域之间的第三区域的表面上。

4. 发明授权

US06720618B2 Power MOSFET device 有权
标题翻译：功率MOSFET器件
公开(公告)号：US06720618B2
公开(公告)日：2004-04-13
申请号：US10055947
申请日：2002-01-28
申请人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
发明人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.
摘要翻译：一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接。

5. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

6. 发明授权

US07026214B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07026214B2
公开(公告)日：2006-04-11
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/00
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

7. 发明授权

US07061048B2 Power MOSFET device 失效
公开(公告)号：US07061048B2
公开(公告)日：2006-06-13
申请号：US10790137
申请日：2004-03-02
申请人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
发明人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L27/96
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

8. 发明申请

US20050056890A1 Offset-gate-type semiconductor device 失效
标题翻译：偏移栅型半导体器件
公开(公告)号：US20050056890A1
公开(公告)日：2005-03-17
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.
摘要翻译：半导体器件包括具有第一导电类型的第一半导体区域，形成在第一半导体区域上并且具有第一导电类型的第二半导体区域，形成在第二半导体区域的表面中并具有第二导电类型的第三半导体区域形成在第二半导体区域的表面上并具有第二导电类型的第四半导体区域以及形成在第二和第四半导体区域上的栅极结构。半导体器件还包括布置在从第四半导体区域的表面延伸到第一半导体区域的沟槽中的导电构件，沟槽具有与栅极结构的侧壁表面齐平的一个侧壁表面。

9. 发明授权

US07663186B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译：半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。

10. 发明授权

US07061060B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07061060B2
公开(公告)日：2006-06-13
申请号：US10388509
申请日：2003-03-17
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

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