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1. 发明申请

US20120262320A1 RESONATOR, DELTA-SIGMA MODULATOR, AND WIRELESS COMMUNICATION DEVICE 有权
标题翻译：谐振器，DELTA-SIGMA调制器和无线通信设备
公开(公告)号：US20120262320A1
公开(公告)日：2012-10-18
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
IPC分类号： H03M3/02 , H03F3/45
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译：两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件连接在每个中间节点和信号输入端子之间。并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。

2. 发明申请

US20110018752A1 FLASH A/D CONVERTER, FLASH A/D CONVERSION MODULE, AND DELTA-SIGMA A/D CONVERTER 审中-公开
标题翻译：闪存A / D转换器，闪存A / D转换模块和DELTA-SIGMA A / D转换器
公开(公告)号：US20110018752A1
公开(公告)日：2011-01-27
申请号：US12899154
申请日：2010-10-06
申请人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
发明人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
IPC分类号： H03M3/00 , H03M1/36
CPC分类号： H03M1/002 , H03M1/208 , H03M1/361
摘要： In a flash A/D converter, a predictor predicts next analog input data based on a digital output signal from an A/D converter, and outputs prediction data. Based on the prediction data from the predictor, a controller turns on comparators having reference voltages near the prediction data, and in order to ensure a certain degree of A/D conversion accuracy even when the prediction fails, also turns on even-numbered comparators 103.2a (where a is 0 to 7), for example. In this manner, even when prediction of next analog input data fails, a 4-bit A/D converter can perform A/D conversion with 3-bit accuracy, while saving power consumption by reducing the number of comparators to be turned on.
摘要翻译：在闪存A / D转换器中，预测器基于来自A / D转换器的数字输出信号预测下一个模拟输入数据，并输出预测数据。基于来自预测器的预测数据，控制器打开具有靠近预测数据的参考电压的比较器，并且即使在预测失败时也确保一定程度的A / D转换精度，也打开偶数比较器103.2 a（其中a为0至7）。以这种方式，即使当下一个模拟输入数据的预测失败时，四位A / D转换器也可以以3位精度执行A / D转换，同时通过减少比较器的数量来导通，从而节省功耗。

3. 发明授权

US08823567B2 Resonator, delta-sigma modulator, and wireless communication device 有权
标题翻译：谐振器，Δ-Σ调制器和无线通信设备
公开(公告)号：US08823567B2
公开(公告)日：2014-09-02
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
IPC分类号： H03M3/00 , H03H11/04
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译：两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件连接在每个中间节点和信号输入端子之间。并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。

4. 发明申请

US20110200077A1 DELTA-SIGMA MODULATOR AND WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译： DELTA-SIGMA调制器和无线通信设备
公开(公告)号：US20110200077A1
公开(公告)日：2011-08-18
申请号：US13094519
申请日：2011-04-26
申请人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
发明人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
IPC分类号： H04B1/38 , H03M3/02
CPC分类号： H03M3/388 , H03M3/424 , H03M3/456
摘要： In a DSM including a loop in which an output signal of a quantizer is digitally processed, and fed back through a DAC to an analog filter, the quantizer quantizes an analog signal from an analog filter section to output a digital signal. The digital signal from the quantizer is digitally processed in a first-order recursive filter circuit including a variable gain amplifier and a delay element. A LUT receives both the digital signal from the quantizer and a table control signal, which is an output signal from the recursive filter circuit, and stores in advance compensation values corresponding to the both signals. A compensation value from the LUT is used to provide a digital output signal compensated for a delay. The digital output signal is converted into an analog signal in the DAC, and then subtracted from an analog input signal in the analog filter section.
摘要翻译：在包括量化器的输出信号被数字处理并通过DAC反馈到模拟滤波器的环路的DSM中，量化器对来自模拟滤波器部分的模拟信号进行量化以输出数字信号。来自量化器的数字信号在包括可变增益放大器和延迟元件的一阶递归滤波器电路中进行数字处理。 LUT接收来自量化器的数字信号和作为来自递归滤波器电路的输出信号的表控制信号，并且预先存储对应于两个信号的补偿值。来自LUT的补偿值用于提供补偿延迟的数字输出信号。数字输出信号在DAC中转换为模拟信号，然后从模拟滤波器部分的模拟输入信号中减去。

5. 发明申请

US20110133964A1 OVERSAMPLING A/D CONVERTER 有权
标题翻译： OVERSAMPLING A / D转换器
公开(公告)号：US20110133964A1
公开(公告)日：2011-06-09
申请号：US13025666
申请日：2011-02-11
申请人： Shiro DOSHO , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro DOSHO , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/12 , H03M3/344 , H03M3/43 , H03M3/454
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.
摘要翻译：过采样A / D转换器包括：第一滤波器，包括第一电阻元件，第一电容元件，第二电阻元件，运算放大器和第二电容元件; 接收第一滤波器的输出的第二滤波器; 第三滤波器，包括第三电阻元件，第三电容元件和第四电阻元件; 量化器，接收第三滤波器的输出并产生数字信号; 以及将数字信号转换成模拟电流信号的D / A转换器。 D / A转换器将产生的模拟电流信号输入到运算放大器的反相输入端。

6. 发明授权

US08922402B2 Offset correction device of comparator 有权
标题翻译：比较器偏移校正装置
公开(公告)号：US08922402B2
公开(公告)日：2014-12-30
申请号：US13564496
申请日：2012-08-01
申请人： Masao Takayama , Kazuo Matsukawa
发明人： Masao Takayama , Kazuo Matsukawa
IPC分类号： H03M1/06 , H03K5/24 , H03M1/10 , H03K3/356 , H03M1/36
CPC分类号： H03M1/1023 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/36
摘要： A comparator offset correction device opens an open switch 205 and closes a short-circuit switch 204 in offset correction of a comparator 201. In this state, a controller 203 allows the comparator 201 to repeat, more than once, the operation of comparing reference voltages 101 input to two input terminals with each other. The filter 202 outputs a frequency signal obtained by smoothing a plurality of comparison results. Based on the frequency signal from the filter 202, the controller 203 outputs a threshold value control signal to the comparator 201 so that the ratio of a high-level voltage to a low-level voltage in the results of the comparison in the comparator 201 is 50%. Thus, even when a current which will be input may differ from a current which is currently input due to, for example, the influence of noise, the threshold value offset amount is normally corrected.
摘要翻译：比较器偏移校正装置打开开关205并在比较器201的偏移校正中闭合短路开关204.在该状态下，控制器203允许比较器201多次重复比较参考电压 101输入到两个输入端子。滤波器202输出通过平滑多个比较结果而获得的频率信号。基于来自滤波器202的频率信号，控制器203向比较器201输出阈值控制信号，使比较器201中的比较结果中的高电平电压与低电平电压的比率为 50％。因此，即使当输入的电流可能与由于例如噪声的影响而当前输入的电流不同时，通常校正阈值偏移量。

7. 发明申请

US20110050476A1 INTEGRATOR, RESONATOR, AND OVERSAMPLING A/D CONVERTER 有权
标题翻译：集成器，谐振器和超滤A / D转换器
公开(公告)号：US20110050476A1
公开(公告)日：2011-03-03
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

8. 发明授权

US07868803B2 Semiconductor device having ΔΣ modulator, and semiconductor system 有权
标题翻译：具有＆Dgr＆amp; 调制器和半导体系统
公开(公告)号：US07868803B2
公开(公告)日：2011-01-11
申请号：US12445357
申请日：2007-10-11
申请人： Shiho Muraki , Naoya Iguchi , Kouichi Nagano , Kazuo Matsukawa , Masao Takayama
发明人： Shiho Muraki , Naoya Iguchi , Kouichi Nagano , Kazuo Matsukawa , Masao Takayama
IPC分类号： H03M3/00
CPC分类号： H03M3/364 , H03M3/424 , H03M3/454
摘要： A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ΔΣ modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ΔΣ modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ΔΣ modulator (13) when the oscillation judgment circuit (7) judges that the ΔΣ modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaining the frequency with which the output of the integrator is outside the normal range, and the oscillation of the ΔΣ modulator (13) is suppressed only when it is oscillated.
摘要翻译：一种半导体器件包括一个溢出检测电路（5），它将至少一个积分器的输出与“ 调制器（13）具有预定值以输出溢出检测信号; 溢出频率计算电路（6），根据上述溢出检测信号，计算作为正常范围以外的积分器的输出频率的溢出频率值，并输出溢出频率值; 振荡判断电路（7），判断“ 调制器（13）基于溢出频率值处于振荡状态; 以及抑制“Dgr”的振荡的振荡停止电路。调制器（13）当振荡判断电路（7）判断为＆Dgr＆调制器处于振荡状态; 其中，通过获得积分器的输出外部的频率，确定积分器的输出是否由于噪声等而暂时超出正常范围，或积分器的输出由于振荡而在正常范围之外正常范围和振荡的＆Dgr＆调制器（13）只有在振荡时被抑制。

9. 发明申请

US20100085228A1 SEMICONDUCTOR DEVICE HAVING AE MODULATOR, AND SEMICONDUCTOR SYSTEM 有权
标题翻译：具有AE调制器的半导体器件和半导体系统
公开(公告)号：US20100085228A1
公开(公告)日：2010-04-08
申请号：US12445357
申请日：2007-10-11
申请人： Shiho Muraki , Naoya Iguchi , Kouichi Nagano , Kazuo Matsukawa , Masao Takayama
发明人： Shiho Muraki , Naoya Iguchi , Kouichi Nagano , Kazuo Matsukawa , Masao Takayama
IPC分类号： H03M3/00
CPC分类号： H03M3/364 , H03M3/424 , H03M3/454
摘要： A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ΔΣ modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ΔΣ modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ΔΣ modulator (13) when the oscillation judgment circuit (7) judges that the ΔΣ modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaining the frequency with which the output of the integrator is outside the normal range, and the oscillation of the ΔΣ modulator (13) is suppressed only when it is oscillated.
摘要翻译：一种半导体器件包括一个溢出检测电路（5），它将至少一个积分器的输出与“ 调制器（13）具有预定值以输出溢出检测信号; 溢出频率计算电路（6），根据上述溢出检测信号，计算作为正常范围以外的积分器的输出频率的溢出频率值，并输出溢出频率值; 振荡判断电路（7），判断“ 调制器（13）基于溢出频率值处于振荡状态; 以及抑制“Dgr”的振荡的振荡停止电路。调制器（13）当振荡判断电路（7）判断为＆Dgr＆调制器处于振荡状态; 其中，通过获得积分器的输出外部的频率，确定积分器的输出是否由于噪声等而暂时超出正常范围，或积分器的输出由于振荡而在正常范围之外正常范围和振荡的＆Dgr＆调制器（13）只有在振荡时被抑制。

10. 发明授权

US08466820B2 Oversampling A/D converter 有权
公开(公告)号：US08466820B2
公开(公告)日：2013-06-18
申请号：US13025666
申请日：2011-02-11
申请人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
IPC分类号： H03M3/00
CPC分类号： H03M1/12 , H03M3/344 , H03M3/43 , H03M3/454
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

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