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1. 发明授权

US07999256B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07999256B2
公开(公告)日：2011-08-16
申请号：US12208595
申请日：2008-09-11
申请人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
发明人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
IPC分类号： H01L23/485 , H01L23/528 , H01L21/66
CPC分类号： H01L23/52 , H01L22/32 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05093 , H01L2224/05554 , H01L2224/056 , H01L2224/06153 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13144 , H01L2224/16 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/4943 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2224/45099 , H01L2924/00
摘要： Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
摘要翻译：电极垫分别具有允许探针接触的探针区域和非探针区域。在排列成两行或更多列的Z字形排列的每个电极焊盘中，用于将另一电极焊盘与内部电路连接的引线互连不直接放置在探针区域的正下方，而是放置在非探针区域的正下方。

2. 发明申请

US20090078935A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090078935A1
公开(公告)日：2009-03-26
申请号：US12208595
申请日：2008-09-11
申请人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
发明人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
IPC分类号： H01L23/50
CPC分类号： H01L23/52 , H01L22/32 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05093 , H01L2224/05554 , H01L2224/056 , H01L2224/06153 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13144 , H01L2224/16 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/4943 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2224/45099 , H01L2924/00
摘要： Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
摘要翻译：电极垫分别具有允许探针接触的探针区域和非探针区域。在排列成两行或更多列的Z字形的每个电极焊盘中，用于将另一电极焊盘与内部电路连接的引线互连不直接放置在探针区域的正下方，而是直接位于非探针区域下方。

3. 发明授权

US08338829B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08338829B2
公开(公告)日：2012-12-25
申请号：US13179331
申请日：2011-07-08
申请人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
发明人： Masao Takahashi , Koji Takemura , Toshihiko Sakashita , Tadaaki Mimura
IPC分类号： H01L23/482 , H01L23/528 , H01L21/66
CPC分类号： H01L23/52 , H01L22/32 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05093 , H01L2224/05554 , H01L2224/056 , H01L2224/06153 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13144 , H01L2224/16 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/4943 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2224/45099 , H01L2924/00
摘要： Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
摘要翻译：电极垫分别具有允许探针接触的探针区域和非探针区域。在排列成两行或更多列的Z字形排列的每个电极焊盘中，用于将另一电极焊盘与内部电路连接的引线互连不直接放置在探针区域的正下方，而是放置在非探针区域的正下方。

4. 发明授权

US07538433B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07538433B2
公开(公告)日：2009-05-26
申请号：US11452957
申请日：2006-06-15
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/52
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

5. 发明申请

US20070001308A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070001308A1
公开(公告)日：2007-01-04
申请号：US11452957
申请日：2006-06-15
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

6. 发明申请

US20070052068A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070052068A1
公开(公告)日：2007-03-08
申请号：US11511306
申请日：2006-08-29
申请人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
摘要翻译：半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。在焊盘下面，第一互连以四边形的平面形状形成。

7. 发明授权

US08810039B2 Semiconductor device having a pad and plurality of interconnects 有权
标题翻译：具有焊盘和多个互连的半导体器件
公开(公告)号：US08810039B2
公开(公告)日：2014-08-19
申请号：US13323454
申请日：2011-12-12
申请人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
IPC分类号： H01L23/48 , H01L23/00 , H01L21/66
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
摘要翻译：半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。在焊盘下面，第一互连以四边形的平面形状形成。

8. 发明申请

US20080036042A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080036042A1
公开(公告)日：2008-02-14
申请号：US11889210
申请日：2007-08-09
申请人： Hikari Sano , Masao Takahashi , Hiroshige Hirano , Koji Takemura
发明人： Hikari Sano , Masao Takahashi , Hiroshige Hirano , Koji Takemura
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.
摘要翻译：半导体器件包括：具有形成在半导体衬底上的功能元件的电路区域; 位于所述电路区域和与所述电路区域间隔开的另一电路区域之间的划线区域，所述划线区域包括切割区域和设置在所述切割区域两侧的非切割区域; 形成在半导体衬底上的划线区域中的第一层间绝缘膜; 由导电材料制成并形成在切割区域中的第一层间绝缘膜中的第一虚设图形; 以及由导电材料制成并形成在每个非切割区域中的第一层间绝缘膜中的第二虚设图案。第一虚设图形的面积与切割区域的面积的单位面积的比率低于第二虚拟图案的面积与非切割区域的面积的每单位面积的比率。

9. 发明授权

US08237281B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08237281B2
公开(公告)日：2012-08-07
申请号：US12984142
申请日：2011-01-04
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/495
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

10. 发明授权

US08102056B2 Semiconductor device having pads and which minimizes defects due to bonding and probing processes 有权
标题翻译：半导体器件具有焊盘并且使由于接合和探测过程引起的缺陷最小化
公开(公告)号：US08102056B2
公开(公告)日：2012-01-24
申请号：US11511306
申请日：2006-08-29
申请人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
摘要翻译：半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。在焊盘下面，第一互连以四边形的平面形状形成。

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