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1. 发明授权

US4716549A Semiconductor memory device having a circuit for compensating for discriminating voltage of memory cells 失效
标题翻译：具有用于补偿存储单元的鉴别电压的电路的半导体存储器件
公开(公告)号：US4716549A
公开(公告)日：1987-12-29
申请号：US901680
申请日：1986-08-29
申请人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Shigeki Nozaki , Kimiaki Sato , Nobumi Kodama
发明人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Shigeki Nozaki , Kimiaki Sato , Nobumi Kodama
IPC分类号： G11C11/407 , G11C11/40 , G11C11/409 , G11C11/4094 , G11C11/4099 , G11C7/02 , G11C11/24
CPC分类号： G11C11/4099 , G11C11/4094
摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.
摘要翻译：一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。

2. 发明授权

US4707811A Semiconductor memory device having extended period for outputting data 失效
标题翻译：具有用于输出数据的延长周期的半导体存储器件
公开(公告)号：US4707811A
公开(公告)日：1987-11-17
申请号：US674313
申请日：1984-11-23
申请人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
IPC分类号： G11C11/401 , G11C7/10 , G11C8/00 , G11C8/04 , G11C8/18 , G11C11/409
CPC分类号： G11C8/04 , G11C7/1024 , G11C7/1033 , G11C8/18
摘要： A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.
摘要翻译：半导体存储器件具有诸如半字节模式或页面模式的操作模式，第一地址选通信号保持在活动状态，并且第二地址选通信号在活动状态和待机状态之间被连续切换，从而使能连续的数据输出。在输出数据之前，根据第二地址选通信号切换到激活状态的先前输出数据被复位一次，而在输出数据之前也执行用于输出的复位操作第一和第二地址选通信号被切换到待机状态，从而扩展数据输出的周期。

3. 发明授权

US4903111A Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US4903111A
公开(公告)日：1990-02-20
申请号：US265275
申请日：1988-10-25
申请人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
IPC分类号： G11C17/14 , G11C17/16 , G11C29/00 , H01L23/525
CPC分类号： G11C29/785 , G11C17/16 , H01L23/5256 , H01L2924/0002
摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.
摘要翻译：一种半导体集成电路器件，具有熔丝熔断型ROM，用于存储关于半导体存储器件等中的有缺陷的位的替换的缺陷位的信息等。集成电路装置包括用于构成ROM的保险丝，用于向保险丝提供熔化电流的焊盘，以及例如由形成在半导体衬底上的半导体衬底和扩散层形成的PN结。通过向连接PN结，熔丝和焊盘的电路施加电压来熔化每个保险丝，使得PN结正向偏置，从而向保险丝提供大电流。

4. 发明授权

US4752914A Semiconductor integrated circuit with redundant circuit replacement 失效
标题翻译：半导体集成电路与冗余电路的更换
公开(公告)号：US4752914A
公开(公告)日：1988-06-21
申请号：US739159
申请日：1985-05-30
申请人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Kimiaki Sato , Norihisa Tsuge , Itaru Tsuge , Sachie Tsuge
发明人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Kimiaki Sato , Norihisa Tsuge , Itaru Tsuge , Sachie Tsuge
IPC分类号： G11C29/00 , G11C8/00 , G11C7/00
CPC分类号： G11C29/835
摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.
摘要翻译：一种半导体集成电路，包括存储单元，用于存储故障电路部分的地址信息，并通过冗余电路部分来替换故障电路部分。半导体集成电路提供用于检测从存储单元读取的数据与接收到的输入地址之间的一致性的比较单元。通过比较单元的比较产生的数据通过外部连接终端传送。

5. 发明授权

US4754313A Semiconductor memory device having stacked-capacitor type memory cells 失效
标题翻译：具有堆叠电容器型存储单元的半导体存储器件
公开(公告)号：US4754313A
公开(公告)日：1988-06-28
申请号：US93128
申请日：1987-09-02
申请人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
IPC分类号： G11C11/401 , G11C11/404 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/02 , H01L29/04 , H01L29/78
CPC分类号： G11C11/404 , H01L21/8221 , H01L27/10808
摘要： A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer. The semiconductor memory device further includes an additional conductive layer directly connected to the other of the source and drain regions of the transfer transistor in the memory cell, through the first insulating layer covering same, and extending over the gate of the adjoining transfer transistors. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. A method for manufacturing a semiconductor memory device having the above construction.
摘要翻译：一种半导体存储器件，包括：衬底; 多个字线; 多个位线; 以及多个存储单元，每个存储单元位于由字线之一和一个位线限定的交点处，并且包括转移晶体管和电容器。每个存储单元具有覆盖转移晶体管的栅极的第一绝缘层。每个存储单元中的电容器包括第二导电层，其通过第一绝缘层接触存储单元中的转移晶体管的源区和漏区之一，并延伸在转移晶体管的栅极上，第二绝缘层形成在第一导电层和在第二绝缘层上延伸的第二导电层。半导体存储器件还包括通过覆盖其的第一绝缘层直接连接到存储单元中的传输晶体管的源极和漏极区域中的另一个的另外的导电层，并且在相邻的转移晶体管的栅极上延伸。每个位线通过附加导电层连接到另一个源极和漏极区域。一种具有上述结构的半导体存储器件的制造方法。

6. 发明授权

US4744061A Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks 失效
标题翻译：具有用于划分的存储单元块的同时测试功能的动态半导体存储器件
公开(公告)号：US4744061A
公开(公告)日：1988-05-10
申请号：US673510
申请日：1984-11-20
申请人： Yoshihiro Takemae , Kimiaki Sato , Masao Nakano , Tomio Nakano
发明人： Yoshihiro Takemae , Kimiaki Sato , Masao Nakano , Tomio Nakano
IPC分类号： G06F12/16 , G06F11/16 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C19/00 , G11C29/00 , G11C29/26 , G11C29/34
CPC分类号： G06F11/167 , G11C11/409 , G11C11/4096 , G11C29/26 , G11C29/70
摘要： A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.
摘要翻译：一种动态半导体存储器件，包括被分成多个块（1-1,1-2）的存储器单元。同时写入使能电路在多个块上同时执行写入操作，并且比较电路将一个块的读取数据与另一个块的读取数据进行比较，从而进行测试。

7. 发明授权

US4970693A Semiconductor memory device with internal control signal based upon output timing 失效
标题翻译：具有基于输出定时的内部控制信号的半导体存储器件
公开(公告)号：US4970693A
公开(公告)日：1990-11-13
申请号：US484474
申请日：1990-02-23
申请人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
发明人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C11/409 , G11C7/22 , G11C8/18 , G11C11/40 , G11C11/413
CPC分类号： G11C7/22 , G11C8/18
摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.
摘要翻译：半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。输出电路具有连接到参考电位线的外部输出端子。输出电路用于产生到外部输出端子的输出。禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

8. 发明授权

US4649406A Semiconductor memory device having stacked capacitor-type memory cells 失效
标题翻译：具有层叠电容器型存储单元的半导体存储器件
公开(公告)号：US4649406A
公开(公告)日：1987-03-10
申请号：US619897
申请日：1984-06-12
申请人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
IPC分类号： G11C11/4097 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4097 , H01L27/10808
摘要： In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.
摘要翻译：在具有层叠电容器型存储单元的半导体存储器件中，每个存储单元的电容器包括基极，绝缘层和对电极。每个存储单元的基极部分重叠而不与其它相邻存储单元的基极接触。

9. 发明授权

US4511997A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4511997A
公开(公告)日：1985-04-16
申请号：US439507
申请日：1982-11-05
申请人： Shigeki Nozaki , Yoshihiro Takemae , Tomio Nakano
发明人： Shigeki Nozaki , Yoshihiro Takemae , Tomio Nakano
IPC分类号： G11C11/419 , G11C11/34 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/40
CPC分类号： G11C11/4096
摘要： A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.
摘要翻译：一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号控制信号线被包括在存储器件中。所有的读出放大器都具有控制信号线和数据总线。

10. 发明授权

US4597059A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4597059A
公开(公告)日：1986-06-24
申请号：US535987
申请日：1983-09-26
申请人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
IPC分类号： G11C11/407 , G11C8/14 , G11C11/408 , G11C7/00
CPC分类号： G11C11/4085 , G11C8/14
摘要： A dynamic semiconductor memory device comprising: (1) one-transistor one-capacitor type memory cells connected between word lines and bit lines and (2) flip-flops, each flip-flop being connected between a pair of word lines to clamp an unselected word line in the pair of word lines to the low voltage of a power source, thereby preventing a subsequent erroneous reading operation as a result of an increase in potential of the unselected word line.
摘要翻译：一种动态半导体存储器件，包括：（1）连接在字线和位线之间的单晶体管单电容型存储单元，以及（2）触发器，每个触发器连接在一对字线之间以钳位未选择的在一对字线中的字线到电源的低电压，从而防止作为未选择字线的电位增加的结果的随后的错误读取操作。

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