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    • 5. 发明授权
    • Information displaying system
    • 信息显示系统
    • US07173634B2
    • 2007-02-06
    • US09853634
    • 2001-05-14
    • Masaaki Nishino
    • Masaaki Nishino
    • G09G5/14
    • G09G5/006G06F3/14G09G2340/12
    • An information displaying system, in which digital information data such as news and a commercial message are displayed with screen data on a display without decreasing the amount of the screen data that are displayed in a working region of the display, is provided. A screen mixing unit mixes digital information data such as news and a commercial message at digital information data adding regions at outside a working region where screen data from a personal computer are displayed on a display with the screen data, without decreasing the screen data in the working region. And the mixed data are converted to data having a frequency being capable of displaying on the display. With this, the digital information data can be displayed with the screen data on the display without decreasing the amount of the screen data that are displayed on the working region on the display. Further, the screen mixing that is conventionally executed in the personal computer is executed in the screen mixing unit in the information displaying system, therefore the load for the personal computer can be reduced.
    • 提供了一种信息显示系统,其中在显示器上显示具有屏幕数据的诸如新闻和商业消息的数字信息数据,而不减少在显示器的工作区域中显示的屏幕数据量。 屏幕混合单元将来自个人计算机的屏幕数据的工作区域外的数字信息数据添加区域上的诸如新闻和商业消息的数字信息数据与屏幕数据混合在一起,而不会减少屏幕数据 工作区域。 并且混合数据被转换为具有能够在显示器上显示的频率的数据。 由此,数字信息数据可以与显示器上的屏幕数据一起显示,而不会减少显示在工作区域上的屏幕数据量。 此外,在个人计算机中通常执行的屏幕混合在信息显示系统中的屏幕混合单元中执行,因此可以减少个人计算机的负担。
    • 9. 发明授权
    • Circuit for generating sampling clock to stably sample a video signal and display apparatus having the circuit
    • 用于产生采样时钟以稳定地采样视频信号的电路和具有该电路的显示装置的电路
    • US06753926B1
    • 2004-06-22
    • US09540880
    • 2000-03-31
    • Masaaki Nishino
    • Masaaki Nishino
    • H04N1100
    • G09G5/008H03L7/06
    • A liquid crystal display apparatus comprises a PLL circuit, a phase adjuster, a picture-data-sampling circuit, a liquid crystal display driver, a video signal processor, and a liquid crystal display panel. The phase adjuster comprises a delay circuit, a comparator, a counter, and a controller. The PLL generates a dot clock which is delayed by the delay circuit by a delay time designated by the controller to be a sampling clock. The counter counts the number of sampling edges of the sampling clock from a negative edge of a horizontal synchronization signal to a positive edge of a binarized video signal supplied from the comparator. The controller observes the number of sampling edges while adjusting the delay to determine the worst sampling clock and sets the best sampling clock whose phase is at a straight angle to the phase of the worst sampling clock.
    • 液晶显示装置包括PLL电路,相位调整器,图像数据采样电路,液晶显示驱动器,视频信号处理器和液晶显示面板。 相位调节器包括延迟电路,比较器,计数器和控制器。 PLL产生点延时延迟延迟电路由控制器指定为采样时钟的延迟时间。 计数器将采样时钟的采样边沿从水平同步信号的下降沿到从比较器提供的二进制化视频信号的上升沿进行计数。 控制器观察采样边沿的数量,同时调整延迟以确定最差采样时钟,并设置最佳采样时钟,其相位与最差采样时钟的相位呈直角。