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1. 发明授权

US07781241B2 Group III-V semiconductor device and method for producing the same 有权
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US07781241B2
公开(公告)日：2010-08-24
申请号：US11987420
申请日：2007-11-29
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Ryohei Inazawa , Toshiya Uemura
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Ryohei Inazawa , Toshiya Uemura
IPC分类号： H01L21/00
CPC分类号： H01L21/8252 , H01L33/0079
摘要： The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.
摘要翻译：本发明的用于制造III-V族半导体器件的方法包括在基底上形成彼此隔离的多个半导体器件，每个半导体器件至少具有靠近基极的n层，并且具有形成在p层顶表面上的p电极和第一低熔点金属扩散防止层，所述低熔点金属扩散防止层形成在所述p层上， p电极的顶表面; 从绝缘材料形成侧面保护膜以覆盖每个半导体器件的侧表面; 通过低熔点金属层将半导体器件接合到导电支撑衬底; 并通过激光剥离过程去除底座。

2. 发明申请

US20080149953A1 Group III-V semiconductor device and method for producing the same 有权
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US20080149953A1
公开(公告)日：2008-06-26
申请号：US11987420
申请日：2007-11-29
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Ryohei Inazawa , Toshiya Uemura
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Ryohei Inazawa , Toshiya Uemura
IPC分类号： H01L21/76 , H01L33/00 , H01L21/02
CPC分类号： H01L21/8252 , H01L33/0079
摘要： The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.
摘要翻译：本发明的用于制造III-V族半导体器件的方法包括在基底上形成彼此隔离的多个半导体器件，每个半导体器件至少具有靠近基极的n层，并且具有形成在p层顶表面上的p电极和第一低熔点金属扩散防止层，所述低熔点金属扩散防止层形成在所述p层上， p电极的顶表面; 从绝缘材料形成侧面保护膜以覆盖每个半导体器件的侧表面; 通过低熔点金属层将半导体器件接合到导电支撑衬底; 并通过激光剥离过程去除底座。

3. 发明授权

US07541262B2 Method for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07541262B2
公开(公告)日：2009-06-02
申请号：US11633622
申请日：2006-12-05
申请人： Masanobu Ando , Toshiya Uemura , Shigemi Horiuchi
发明人： Masanobu Ando , Toshiya Uemura , Shigemi Horiuchi
IPC分类号： H01L21/30
CPC分类号： H01L33/0079 , H01L33/32 , H01L33/38 , H01L33/40
摘要： The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica filler particles (diameter: about 2 to about 4 μm) are added to the base material in an appropriate amount. Charging of the second adhesive may be performed by adding the adhesive dropwise to a side wall of a semiconductor wafer, or by immersing an edge of the semiconductor wafer in the adhesive in the form of liquid. When a liquid-form epoxy material of low viscosity is employed, the spaces can be evenly filled with the second adhesive by capillary action. An n-electrode is formed on an exposed surface of an n-type layer through vapor deposition employing a resist mask. Separation trenches are formed through half-cut dicing from the exposed surface of the n-type layer toward the second adhesive.
摘要翻译：本发明考虑防止用于在半导体晶片中形成分离沟槽的切割机的堵塞，并且还提高从半导体晶片切出的半导体器件的产量。要填充到空间中的第二粘合剂包含环氧树脂材料作为基材。将二氧化硅填料颗粒（直径：约2至约4μm）以适当的量加入到基材中。第二粘合剂的充电可以通过将粘合剂滴加到半导体晶片的侧壁，或者通过将半导体晶片的边缘以液体的形式浸入粘合剂中来进行。当使用低粘度的液态环氧材料时，可以通过毛细作用将间隙均匀地填充第二粘合剂。通过使用抗蚀剂掩模的气相沉积在n型层的暴露表面上形成n电极。通过从n型层的暴露表面朝向第二粘合剂的半切割切割形成分离沟槽。

4. 发明申请

US20070141807A1 Method for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20070141807A1
公开(公告)日：2007-06-21
申请号：US11633622
申请日：2006-12-05
申请人： Masanobu Ando , Toshiya Uemura , Shigemi Horiuchi
发明人： Masanobu Ando , Toshiya Uemura , Shigemi Horiuchi
IPC分类号： H01L21/30
CPC分类号： H01L33/0079 , H01L33/32 , H01L33/38 , H01L33/40
摘要： The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica filler particles (diameter: about 2 to about 4 μm) are added to the base material in an appropriate amount. Charging of the second adhesive may be performed by adding the adhesive dropwise to a side wall of a semiconductor wafer, or by immersing an edge of the semiconductor wafer in the adhesive in the form of liquid. When a liquid-form epoxy material of low viscosity is employed, the spaces can be evenly filled with the second adhesive by capillary action. An n-electrode is formed on an exposed surface of an n-type layer through vapor deposition employing a resist mask. Separation trenches are formed through half-cut dicing from the exposed surface of the n-type layer toward the second adhesive.
摘要翻译：本发明考虑防止用于在半导体晶片中形成分离沟槽的切割机的堵塞，并且还提高从半导体晶片切出的半导体器件的产量。要填充到空间中的第二粘合剂包含环氧树脂材料作为基材。将二氧化硅填料颗粒（直径：约2至约4μm）以适当的量加入到基材中。第二粘合剂的充电可以通过将粘合剂滴加到半导体晶片的侧壁，或者将半导体晶片的边缘以液体的形式浸入粘合剂中来进行。当使用低粘度的液态环氧材料时，可以通过毛细作用将间隙均匀地填充第二粘合剂。通过使用抗蚀剂掩模的气相沉积在n型层的暴露表面上形成n电极。通过从n型层的暴露表面朝向第二粘合剂的半切割切割形成分离沟槽。

5. 发明申请

US20070138540A1 Group III nitride based compound semiconductor optical device 审中-公开
标题翻译： III族氮化物基化合物半导体光学器件
公开(公告)号：US20070138540A1
公开(公告)日：2007-06-21
申请号：US11633621
申请日：2006-12-05
申请人： Toshiya Uemura , Shigemi Horiuchi , Masanobu Ando
发明人： Toshiya Uemura , Shigemi Horiuchi , Masanobu Ando
IPC分类号： H01L29/792
CPC分类号： H01L33/405 , H01L33/0079 , H01L33/32 , H01S5/0213 , H01S5/0217 , H01S5/32341
摘要： An object of the invention is to prevent defoliation of a first electrode layer of the device of the invention including a high-reflectance metal layer. In the group III nitride based compound semiconductor optical device of the invention, an electrode formed on a p-type layer has a first electrode layer which is formed from high-reflectance rhodium (Rh) and which is directly joined to the p-type layer, and a second electrode layer which is formed from titanium (Ti) having reactivity with nitrogen and which is provided so as to cover the first electrode layer, and a portion of the second electrode layer is joined to the uppermost layer of the group III nitride based compound semiconductor.
摘要翻译：本发明的目的是防止包括高反射率金属层的本发明的器件的第一电极层脱落。在本发明的III族氮化物系化合物半导体光学元件中，形成在p型层上的电极具有由高反射率铑（Rh）形成的第一电极层，其与p型层直接接合以及第二电极层，其由与氮反应性的钛（Ti）形成，并且被设置为覆盖第一电极层，并且第二电极层的一部分接合到III族氮化物的最上层基复合半导体。

6. 发明授权

US08420502B2 Group III-V semiconductor device and method for producing the same 有权
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US08420502B2
公开(公告)日：2013-04-16
申请号：US12656970
申请日：2010-02-22
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
IPC分类号： H01L21/20 , H01L21/18
CPC分类号： H01L33/025 , H01L33/0079 , H01L33/46
摘要： A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.
摘要翻译：一种制造III-V族半导体器件的方法，包括在基底上形成彼此隔离的多个半导体器件，通过离子注入形成每个半导体器件的侧表面的表面层中的高电阻区域半导体器件，在形成高电阻区域之后，在半导体器件的顶表面上形成p电极和低熔点金属扩散防止层，通过低电阻区域将半导体器件接合到导电支撑衬底，熔点金属层，并通过激光剥离工艺去除基体。

7. 发明申请

US20080237629A1 Group III-V Semiconductor device and method for producing the same 审中-公开
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US20080237629A1
公开(公告)日：2008-10-02
申请号：US12076234
申请日：2008-03-14
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
IPC分类号： H01L33/00
CPC分类号： H01L33/025 , H01L33/0079 , H01L33/46
摘要： A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.
摘要翻译：接合到导电支撑基板的III-V族半导体器件，该器件具有其表面具有通过离子注入形成的高电阻区域的侧表面。

8. 发明申请

US20100151612A1 Group III-V semiconductor device and method for producing the same 有权
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US20100151612A1
公开(公告)日：2010-06-17
申请号：US12656970
申请日：2010-02-22
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
IPC分类号： H01L21/20 , H01L21/18
CPC分类号： H01L33/025 , H01L33/0079 , H01L33/46
摘要： A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.
摘要翻译：一种制造III-V族半导体器件的方法，包括在基底上形成彼此隔离的多个半导体器件，通过离子注入形成每个半导体器件的侧表面的表面层中的高电阻区域半导体器件，在形成高电阻区域之后，在半导体器件的顶表面上形成p电极和低熔点金属扩散防止层，通过低电阻区域将半导体器件接合到导电支撑衬底，熔点金属层，并通过激光剥离工艺去除基体。

9. 发明授权

US07005684B2 Group III nitride based semiconductor luminescent element 有权
标题翻译： III族氮化物基半导体发光元件
公开(公告)号：US07005684B2
公开(公告)日：2006-02-28
申请号：US10479602
申请日：2002-06-03
申请人： Toshiya Uemura , Shigemi Horiuchi
发明人： Toshiya Uemura , Shigemi Horiuchi
IPC分类号： H01L29/22
CPC分类号： H01L33/40 , H01L33/32 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/05573 , H01L2224/14 , H01L2224/16145 , H01L2224/16225 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/05644 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171
摘要： In a flip chip type Group III nitride compound semiconductor light-emitting element, an Au layer is provided on each of a surface of a p-side electrode and a surface of an n-side electrode with interposition of a Ti layer.
摘要翻译：在倒装芯片型III族氮化物化合物半导体发光元件中，在p侧电极的表面和具有Ti层的n侧电极的表面的每一个上设置Au层。

10. 发明申请

US20070141806A1 Method for producing group III nitride based compound semiconductor device 审中-公开
标题翻译：制备III族氮化物基化合物半导体器件的方法
公开(公告)号：US20070141806A1
公开(公告)日：2007-06-21
申请号：US11633619
申请日：2006-12-05
申请人： Toshiya Uemura , Shigemi Horiuchi
发明人： Toshiya Uemura , Shigemi Horiuchi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L33/40 , H01L33/32
摘要： The present invention relates to method for producing a group III nitride based compound semiconductor device. A plurality of group III nitride based compound semiconductor layers are epitaxially grown on a first substrate. An electrode is formed on the uppermost layer of the group III nitride based compound semiconductor layers, the electrode being formed of a first multi-layer including at least a layer for preventing migration of tin contained in a solder. A second multi-layer including at least a layer for preventing migration of tin contained in a solder is formed on a second substrate on which a semiconductor device is to be placed. The surface of the first substrate on which the electrode has been formed is joined to the surface of the second substrate on which the multi-layer has been formed by means of a solder containing at least tin. the first substrate removed from the group III nitride based compound semiconductor layers.
摘要翻译：本发明涉及制备III族氮化物基化合物半导体器件的方法。在第一基板上外延生长多个III族氮化物基化合物半导体层。在III族氮化物基化合物半导体层的最上层形成电极，该电极由至少包含防止锡中所含锡迁移的第一多层形成。在其上放置半导体器件的第二基板上形成至少包括用于防止焊料中所含锡迁移的层的多层。已经形成有电极的第一基板的表面通过至少含有锡的焊料接合到已经形成多层的第二基板的表面上。从III族氮化物基化合物半导体层去除第一衬底。

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