专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06351291B1 Image processing apparatus for an on-screen-display which displays one image over another image 有权
标题翻译：用于屏幕显示的图像处理装置，其在另一图像上显示一个图像
公开(公告)号：US06351291B1
公开(公告)日：2002-02-26
申请号：US09537389
申请日：2000-03-29
申请人： Masanari Asano
发明人： Masanari Asano
IPC分类号： H04N5445
CPC分类号： H04N5/45 , H04N5/44504 , H04N21/4316
摘要： An image processing apparatus comprises an image memory comprising a first storing area for storing first image data for a background and a second storing area for storing second image data for an on-screen-display; a display buffer memory for storing data in a format used for display based on the first and second image data read from the image memory; and a controller for controlling accesses to the image memory and the display buffer memory, the controller reading the first image data from the first storing area in the image memory and writing the first image data into the display buffer memory and reading the second image data from the second storing area in the image memory and writing the second image data into a designated area in the display buffer memory.
摘要翻译：图像处理装置包括：图像存储器，包括用于存储用于背景的第一图像数据的第一存储区域和用于存储用于屏幕显示的第二图像数据的第二存储区域; 显示缓冲存储器，用于基于从图像存储器读取的第一和第二图像数据存储用于显示的格式的数据; 以及控制器，用于控制对图像存储器和显示缓冲存储器的访问，所述控制器从图像存储器中的第一存储区域读取第一图像数据，并将第一图像数据写入显示缓冲存储器并从第图像存储器中的第二存储区域，并将第二图像数据写入显示缓冲存储器中的指定区域。

2. 发明授权

US07336286B2 Method of and an apparatus for processing images 有权
标题翻译：图像处理方法和装置
公开(公告)号：US07336286B2
公开(公告)日：2008-02-26
申请号：US09899157
申请日：2001-07-06
申请人： Masanari Asano
发明人： Masanari Asano
IPC分类号： G09G5/00
CPC分类号： H04N5/45 , G09G5/393 , G09G5/395 , G09G2340/0407 , G09G2340/125 , H04N5/44504
摘要： In an image processing apparatus to conduct an on-screen display operation, the bus band of an image memory is minimized. The apparatus includes an image memory including a first memory area to store a first image data group of a first image for a background and a second memory area for storing a second image data group of a second image for an on-screen display, a display buffer memory for storing, in a format to be displayed on a display screen, the first image and the second image read from the image memory; and a control section for controlling accesses in the image memory and the display buffer memory, for reading the first image data group from the first memory area and writing the first image data group in the display buffer memory, and for reading the second image data group from the second memory area and writing the second image data group in a specified area of the display buffer memory. The control section includes a data expansion control section capable of increasing a data amount of the second image data group read from the image memory, according to the second image data group.
摘要翻译：在进行屏幕显示操作的图像处理装置中，图像存储器的总线频带被最小化。该装置包括图像存储器，其包括存储用于背景的第一图像的第一图像数据组的第一存储区域和用于存储用于屏幕显示的第二图像的第二图像数据组的第二存储区域，显示器缓冲存储器，用于以显示在显示屏幕上的格式存储从图像存储器读取的第一图像和第二图像; 以及用于控制图像存储器和显示缓冲存储器中的访问的控制部分，用于从第一存储区域读取第一图像数据组并将第一图像数据组写入显示缓冲存储器中，并用于读取第二图像数据组并且将第二图像数据组写入显示缓冲存储器的指定区域。控制部包括能够根据第二图像数据组增加从图像存储器读取的第二图像数据组的数据量的数据扩展控制部。

3. 发明授权

US07173629B2 Image processor with the closed caption function and image processing method 失效
标题翻译：图像处理器具有隐藏字幕功能和图像处理方法
公开(公告)号：US07173629B2
公开(公告)日：2007-02-06
申请号：US09813035
申请日：2001-03-21
申请人： Masanari Asano
发明人： Masanari Asano
IPC分类号： G06G12/00
CPC分类号： H04N7/035 , G09G5/39 , G09G2360/12 , H04N5/44504 , H04N21/4435 , H04N21/488 , H04N21/4884 , H04N21/4888
摘要： A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.
摘要翻译：存储器控制单元使用存储器控制器来调整和设置存储器的存储空间中的图像数据区域的地址和与存储区域相邻的窗口区域的地址。存储器控制单元存储在指定的地址位置处提供的图像数据以外的数据，并且当控制信号被发送到存储器时，从存储器读出包括存储在窗口区域中的数据的图像数据。在消隐期间将从窗口区读出的数据插入预定位置。

4. 发明授权

US06014467A High speed, high precision image compression 失效
标题翻译：高速，高精度图像压缩
公开(公告)号：US06014467A
公开(公告)日：2000-01-11
申请号：US932750
申请日：1997-09-17
申请人： Masanari Asano
发明人： Masanari Asano
IPC分类号： G06T9/00 , G06K9/36 , G06K9/46
CPC分类号： G06T9/007
摘要： An image compression system having: an image data supply unit for supplying image data divided into a block unit; a DCT unit for discrete-cosine-transforming the image data in the block unit supplied from the image data supply unit to generate DCT coefficients in the block unit; a coded data generating unit for successively generating coded data of the DCT coefficients at first and second compression factors each time the DCT coefficients of one block are generated by the DCT unit; a counter unit for accumulating the amount of coded data generated at each of the first and second compression factors by the coded data generating unit; and a compression factor estimating unit for estimating a compression factor suitable for generating coded data of a target amount, in accordance with the amounts of coded data accumulated at the first and second compression factors by the counter unit.
摘要翻译：一种图像压缩系统，具有：图像数据提供单元，用于提供划分成块单元的图像数据; DCT单元，用于对从图像数据提供单元提供的块单元中的图像数据进行离散余弦变换，以产生块单元中的DCT系数; 编码数据生成单元，每当DCT单元产生一个块的DCT系数时，依次产生第一和第二压缩因子的DCT系数的编码数据; 计数器单元，用于累积由编码数据生成单元在第一和第二压缩因子中的每一个生成的编码数据量; 以及压缩因子估计单元，用于根据由计数器单元在第一和第二压缩因子处累积的编码数据的量来估计适于产生目标量的编码数据的压缩因子。

5. 发明授权

US5361220A Discrete cosine transformation with reduced components 失效
标题翻译：具有减少分量的离散余弦变换
公开(公告)号：US5361220A
公开(公告)日：1994-11-01
申请号：US982623
申请日：1992-11-27
申请人： Masanari Asano
发明人： Masanari Asano
IPC分类号： G06F17/14 , G06F15/332
CPC分类号： G06F17/147
摘要： A discrete cosine transformation processor includes first and second one-dimensional discrete cosine transformation circuits, a pre-processing circuit connected to the input of the one-dimensional discrete cosine processing circuit, and a post-processing circuit connected to the output of the one-dimensional discrete cosine processing circuit. The pre-processing circuit of the first one-dimensional discrete cosine processing circuit and the post-processing circuit of said second one-dimensional discrete cosine transformation circuit includes a shared first butterfly circuit, and the post-processing circuit of the first one-dimensional discrete cosine transformation circuit and the pre-processing circuit of the second one-dimensional discrete cosine transformation circuit includes a shared second butterfly circuit. A look-up table is used for two bits of each of two elements to a DCT matrix. The shared portion of the look-up tables can be extended for use with the forward and inverse DCT processing. A discrete cosine transformation processor includes a calculation block for sequentially performing a calculation for a predetermined bit position of each of a set of input signals, an adder/subtracter connected to the calculation block, a shift register for sequentially storing the established portion of an output signal of the adder/subtracter, and a resister for sequentially storing the carry portion used for the addition/subtraction at the next calculation cycle.
摘要翻译：离散余弦变换处理器包括第一和第二一维离散余弦变换电路，连接到一维离散余弦处理电路的输入的预处理电路，以及连接到单维离散余弦变换电路的输出的后处理电路，二维离散余弦处理电路。第一一维离散余弦处理电路的预处理电路和所述第二一维离散余弦变换电路的后处理电路包括共享的第一蝶形电路和第一一维离散余弦变换电路的后处理电路离散余弦变换电路和第二一维离散余弦变换电路的预处理电路包括共享的第二蝶形电路。查找表用于DCT矩阵的两个元素中的每一个的两位。可以将查找表的共享部分扩展为用于正向和反向DCT处理。离散余弦变换处理器包括用于顺序执行一组输入信号中的每一个的预定位位置的计算块，连接到计算块的加法器/减法器，用于顺序存储输出的建立部分的移位寄存器加法器/减法器的信号，以及用于在下一个计算周期顺序地存储用于加/减的进位部分的寄存器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式