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1. 发明授权

US06483714B1 Multilayered wiring board 失效
标题翻译：多层接线板
公开(公告)号：US06483714B1
公开(公告)日：2002-11-19
申请号：US09511517
申请日：2000-02-23
申请人： Masanao Kabumoto , Yoshihiro Nabe , Masaru Nomoto , Shigeto Takeda
发明人： Masanao Kabumoto , Yoshihiro Nabe , Masaru Nomoto , Shigeto Takeda
IPC分类号： H05K702
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/66 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H01L2924/3025 , H05K1/0289 , H01L2224/0401
摘要： A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed thereon, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure consisting essentially of a third insulating layer having a third parallel conductor array crossing at an angle of 30 to 60 degrees to the first parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermediate insulating layer having a conductive layer, and the first or second parallel conductor array and the third or fourth parallel conductor array are electrically interconnected by a third through conductor array.
摘要翻译：一种多层布线板，包括第一层叠结构，其基本上由第一绝缘层和第二绝缘层构成，第一绝缘层具有第一平行导体阵列和形成在其上的第二绝缘层，具有与第一平行导体阵列垂直的第二平行导体阵列，第一和第二平行导体阵列通过第一通孔导体阵列电互连; 以及第二层叠结构，其基本上由具有与第一平行导体阵列以30度至60度的角度交叉的第三平行导体阵列的第三绝缘层和形成在第三绝缘层的顶部上的第四绝缘层组成，与第三平行导体阵列正交的平行导体阵列，第三和第四平行导体阵列通过第二通孔导体阵列电互连，其中第二堆叠结构通过插入在第一叠层结构之间而形成具有导电性的中间绝缘层层，并且第一或第二平行导体阵列和第三或第四平行导体阵列通过第三贯通导体阵列电互连。

2. 发明申请

US20050079098A1 Microchemical chip 审中-公开
标题翻译：微化学芯片
公开(公告)号：US20050079098A1
公开(公告)日：2005-04-14
申请号：US10877951
申请日：2004-06-24
申请人： Shin Matsuda , Kuninori Yokomine , Katsuhiko Onitsuka , Masanao Kabumoto
发明人： Shin Matsuda , Kuninori Yokomine , Katsuhiko Onitsuka , Masanao Kabumoto
IPC分类号： B01J19/00 , G01N31/22
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/0086 , B01J2219/00862 , B01J2219/00873 , B01J2219/00889 , B01J2219/00891 , B01J2219/00959 , B01J2219/00961
摘要： A microchemical chip includes a base having a channel for causing fluids to-be-treated to flow therethrough, and supply portions connected to the channel, for causing the fluids to-be-treated to flow into the channel, respectively. In the microchemical chip, a plurality of fluids to-be-treated are respectively caused to flow from the supply portions into the channel, and the plurality of fluids to-be-treated caused to flow in are merged to be subjected to chemical reactions. In the microchemical chip, heaters are formed for heating the fluid to-be-treated flowing through supply channels of the supply portions.
摘要翻译：微化学芯片包括具有用于使待处理的流体流过其中的通道的底座，以及连接到通道的供应部分，用于使被处理流体分别流入通道。在微化学芯片中，分别使待处理的多种流体从供给部流入通道，并且流入待处理的多种流体被合并以进行化学反应。在微化学芯片中，形成加热器以加热流经供应部分的供应通道的待处理流体。

3. 发明申请

US20070222052A1 WIRING STRUCTURE, MULTILAYER WIRING BOARD, AND ELECTRONIC DEVICE 审中-公开
标题翻译：接线结构，多层接线板和电子设备
公开(公告)号：US20070222052A1
公开(公告)日：2007-09-27
申请号：US11690482
申请日：2007-03-23
申请人： Masanao Kabumoto
发明人： Masanao Kabumoto
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/49822 , H01L23/66 , H01L2223/6627 , H01L2223/6638 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H01P3/08 , H05K1/0224 , H05K1/0245 , H05K1/0253 , H05K1/0298 , H05K2201/09236 , H05K2201/093 , H05K2201/0969 , H01L2924/00
摘要： A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance from the general signal line and the differential signal line, and has a non-formed portion in a region to be electromagnetically coupled to the differential signal line.
摘要翻译：布线结构包括通用信号线，具有一对信号布线和参考电位层的差分信号线。信号线分别发送波形彼此反转的差分信号。参考电位层被布置成与一般信号线和差分信号线具有一定距离，并且在要被电磁耦合到差分信号线的区域中具有非形成部分。

4. 发明授权

US06707685B2 Multi-layer wiring board 失效
标题翻译：多层接线板
公开(公告)号：US06707685B2
公开(公告)日：2004-03-16
申请号：US10132685
申请日：2002-04-25
申请人： Masanao Kabumoto , Kouki Kawabata
发明人： Masanao Kabumoto , Kouki Kawabata
IPC分类号： H05K706
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2223/6627 , H01L2224/16 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/0289 , H05K1/0298 , H05K2201/0187 , H05K2201/09672
摘要： A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.
摘要翻译：多层布线基板包括绝缘基板，该绝缘基板在其顶表面的中心部分具有半导体器件安装部分，并且在其下表面上具有外部电极。绝缘基板包括具有第一组平行布线的多层布线; 与其正交布置的第二组平行布线; 以及一组用于在它们之间提供电连接的通孔导体。通过内部形成的电容器将功率从外部电极提供给半导体器件。内置电容器并联连接，其在从半导体器件的工作频带到谐波分量的频带范围内以及在不同谐振频率之间出现的反共振频率范围内具有不同的谐振频率，a 复合阻抗等于或低于预定值。

5. 发明授权

US5883428A Package for housing a semiconductor element 失效
标题翻译：用于容纳半导体元件的封装
公开(公告)号：US5883428A
公开(公告)日：1999-03-16
申请号：US893138
申请日：1997-07-15
申请人： Masanao Kabumoto , Masaaki Hori , Tetsuo Hirakawa
发明人： Masanao Kabumoto , Masaaki Hori , Tetsuo Hirakawa
IPC分类号： H01L25/00 , H01L23/50 , H01L25/16 , H01L29/00 , H01L23/52 , H01L23/48
CPC分类号： H01L23/50 , H01L25/165 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01012 , H01L2924/0102 , H01L2924/01025 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/15192 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/19041 , H01L2924/19106 , H01L2924/30107
摘要： A semiconductor element-housing package, comprising an insulating substrate composed of a plurality of laminated insulating layers and having a mounting portion for mounting a semiconductor element, in the center of a top surface thereof; a ground bonding pad and a power-supply bonding pad formed on the top surface of the insulating substrate, at the periphery of the semiconductor element-mounting portion, to which a ground electrode and a power-supply electrode of the semiconductor element are connected; and a pair of capacitor-connecting pads, formed on the underside of the insulating substrate, one of which is connected to the ground bonding pad, the other of which is connected to the power-supply bonding pad, and to both of which electrodes of a chip capacitor are connected, characterized by having a ground plane and a power-supply plane sandwiching at least one of the insulating layers buried opposing each other within the insulating substrate, and having electrical connections from the ground plane and the power-supply plane to the ground bonding pad and the power-supply bonding pad, respectively, at the periphery of the semiconductor element-mounting portion of the insulating substrate, to thereby downsize the package and to produce a satisfactory, noise-reducing effect.
摘要翻译：一种半导体元件外壳封装，包括由多个层叠绝缘层构成的绝缘基板，并且具有用于安装半导体元件的安装部分在其顶表面的中心; 在所述半导体元件安装部的周围形成有与所述半导体元件的接地电极和电源电极连接的绝缘基板的上表面的接地焊盘和电源接合焊盘; 以及形成在绝缘基板的下侧上的一对电容器连接焊盘，其中一个连接到接地焊盘，另一个连接到电源焊盘，并且连接到两个电极连接芯片电容器，其特征在于具有接地面和电源平面，所述电源平面将绝缘衬底内相互掩埋的绝缘层中的至少一个相互夹在中间，并且具有从接地平面和供电平面到接地焊盘和电源接合焊盘，分别在绝缘基板的半导体元件安装部分的周围，从而减小封装尺寸并产生令人满意的降噪效果。

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