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    • 2. 发明授权
    • Method of etching insulating film and method of forming interconnection layer
    • 蚀刻绝缘膜的方法和形成互连层的方法
    • US06638848B1
    • 2003-10-28
    • US09517731
    • 2000-03-02
    • Masanaga FukasawaShingo Kadomura
    • Masanaga FukasawaShingo Kadomura
    • H01L214763
    • H01L21/76801H01L21/28556H01L21/31116H01L21/31138H01L21/76802
    • A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film having a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.
    • 一种在不形成损伤层的情况下快速蚀刻包括有机基电介质膜的绝缘膜的方法,或者导致生产量下降的方法,包括形成包括有机基电介质膜的绝缘膜的步骤,例如具有 聚芳醚膜或其它有机基介电膜和氧化硅基介电膜或其它绝缘膜,通过在绝缘膜上方图案化形成掩模层,并且当蚀刻有机基介电膜部分时,使用含有NH的离子或自由基 在氢气和氮气的混合气体中通过气体放电产生的组,或者使用掩模层作为蚀刻掩模的氨气的混合气体蚀刻绝缘层并形成开口等,同时产生含有CN基团的反应产物 。
    • 4. 发明授权
    • Damascene interconnection having porous low k layer with a hard mask reduced in thickness
    • 具有厚度减小的具有多孔低k层的硬质掩模的镶嵌互连
    • US07300868B2
    • 2007-11-27
    • US11394011
    • 2006-03-30
    • Masanaga FukasawaTakeshi Nogami
    • Masanaga FukasawaTakeshi Nogami
    • H01L21/4763
    • H01L21/76829H01L21/76807H01L21/7684H01L21/76849H01L23/53238H01L2924/0002H01L2924/00
    • A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.
    • 提供了一种制造镶嵌互连的方法。 该方法开始于在衬底上形成第一电介质层,第一电介质子层上的覆盖层和覆盖层上的抗蚀剂图案以限定第一互连开口。 通过抗蚀剂图案蚀刻覆盖层和电介质层以形成第一互连开口。 去除抗蚀剂图案,并且在封盖层和第一互连开口中施加阻挡层。 通过用导电材料填充第一互连开口形成互连。 互连被平坦化以去除多余的材料,并且选择性地蚀刻由平坦化步骤损坏的第一介电层的一部分。 施加第二介电层以代替第一电介质的损坏部分。
    • 7. 发明申请
    • Damage recovery method for low K layer in a damascene interconnection
    • 在大马士革互连中的低K层的损伤恢复方法
    • US20070232047A1
    • 2007-10-04
    • US11395829
    • 2006-03-31
    • Masanaga FukasawaTakeshi Nogami
    • Masanaga FukasawaTakeshi Nogami
    • H01L21/44
    • H01L21/3105H01L21/31058H01L21/76807H01L21/76814H01L21/76826
    • A method of fabricating a damascene interconnection is provided. The method begins by forming on a substrate a low k dielectric layer and a resist pattern over the low k dielectric layer to define a first interconnect opening. The low k dielectric layer is etched through the resist pattern to form the first interconnect opening, whereby damage arises to a portion of the low k dielectric layer defining a sidewall of the first interconnect opening. The resist pattern is then removed and a barrier layer is applied to line the first interconnect opening. An interconnection is formed by filling the first interconnect opening with a conductive material. The interconnection is planarized to remove excess material, whereby an underlying portion of the low k dielectric layer is damaged during planarizing. The damaged underlying portion of the low k dielectric layer and the damaged sidewall portion of the low k dielectric layer are both repaired at least in part after performing the planarizing step.
    • 提供了一种制造镶嵌互连的方法。 该方法开始于在衬底上形成低k电介质层和在低k电介质层上的抗蚀剂图案以限定第一互连开口。 通过抗蚀剂图案蚀刻低k电介质层以形成第一互连开口,由此限定第一互连开口的侧壁的低k电介质层的一部分产生损伤。 然后去除抗蚀剂图案,并且施加阻挡层以使第一互连开口线对。 通过用导电材料填充第一互连开口形成互连。 互连被平坦化以去除多余的材料,由此低k电介质层的下层部分在平坦化期间被损坏。 在执行平坦化步骤之后,至少部分地修复低k电介质层的损坏的底层部分和低k电介质层的损坏的侧壁部分。