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1. 发明授权

US4804869A BiMOS logical circuit 失效
标题翻译： BiMOS逻辑电路
公开(公告)号：US4804869A
公开(公告)日：1989-02-14
申请号：US106429
申请日：1987-10-09
申请人： Masami Masuda , Yasumitsu Nozawa , Takayuki Kawaguchi
发明人： Masami Masuda , Yasumitsu Nozawa , Takayuki Kawaguchi
IPC分类号： H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H03K17/56 , H03K19/08 , H03K19/0944 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448
摘要： The invention is a BiMOS logical circuit having a reduced number of components and increased operating speed. First and second MOS transistors are provided for, respectively, driving first and second bipolar transistors. The gates of these MOS transistors are, respectively, connected to the bases of the second and first bipolar transistors. The input terminal is connected to the gates of the MOS transistors.
摘要翻译：本发明是一种BiMOS逻辑电路，其具有减少的部件数量和增加的操作速度。第一和第二MOS晶体管分别用于驱动第一和第二双极晶体管。这些MOS晶体管的栅极分别连接到第二和第一双极晶体管的基极。输入端子连接到MOS晶体管的栅极。

2. 发明授权

US4804868A BiMOS logical circuit 失效
标题翻译： BiMOS逻辑电路
公开(公告)号：US4804868A
公开(公告)日：1989-02-14
申请号：US106362
申请日：1987-10-09
申请人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
发明人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
IPC分类号： H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H03K17/56 , H03K19/08 , H03K19/0944 , H03K19/096 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0963
摘要： This invention is a BiMOS logical circuit that provides a suitable output level with a limited number of components. The intermediate node of a PMOS transistor and an NMOS transistor is connected to the base of a bipolar transistor to control output voltage. The NMOS transistor is connected between the output terminal and the power source, and an output voltage approximately equal to the power supply voltage is obtained at the output terminal.
摘要翻译：本发明是一种BiMOS逻辑电路，其提供具有有限数量的组件的合适的输出电平。 PMOS晶体管的中间节点和NMOS晶体管连接到双极晶体管的基极以控制输出电压。 NMOS晶体管连接在输出端子与电源之间，在输出端子处获得大致等于电源电压的输出电压。

3. 发明授权

US6018488A Semiconductor memory device and method relieving defect of semiconductor memory device 失效
标题翻译：半导体存储器件和解决半导体存储器件缺陷的方法
公开(公告)号：US6018488A
公开(公告)日：2000-01-25
申请号：US104626
申请日：1998-06-25
申请人： Akihiro Mishima , Yoichi Suzuki , Yasumitsu Nozawa , Masami Masuda
发明人： Akihiro Mishima , Yoichi Suzuki , Yasumitsu Nozawa , Masami Masuda
IPC分类号： G11C7/00
CPC分类号： G11C7/00
摘要： A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit lines are provided two pieces at each bit. Between the MOS transistors Q1, Q2 for pre-charge and the bit lines driving power supply terminal Vcc, three pieces of the fuses F1-F3 are connected at each column. When the leak defect occurs to the bit lines, all of the fuses F1-F3 connected to the bit lines are cut. Further, a semiconductor memory device includes a plurality of section regions, a redundancy circuit RD1 which replaces a defective cell at each section region, a redundancy circuit RD2 which replaces the defective cell at each row address. The section regions are provided at each address in the column direction. In each section region, cell ground power supply lines Vss are formed circularly. Outside each section region a pad ground power supply line Vss' are formed. Each of the cell ground power supply lines Vss and the pad ground power supply line Vss' are connected via a plurality of fuses F connected in parallel.
摘要翻译：半导体存储器件包括纵向和纵向布置的位线和字线，能够读出和写入的用于预充电的MOS晶体管Q1和Q2，用于短路的MOS晶体管Q3和用于短路的MOS晶体管Q3的晶体管Q4和Q5 设置电压电平。位线在每个位都提供两段。在用于预充电的MOS晶体管Q1，Q2和位线驱动电源端子Vcc之间，在每列连接三个保险丝F1-F3。当位线发生泄漏故障时，连接到位线的所有保险丝F1-F3被切断。此外，半导体存储器件包括多个部分区域，替换每个部分区域的有缺陷的单元的冗余电路RD1，替代每个行地址处的有缺陷单元的冗余电路RD2。在列方向的每个地址处设置区域区域。在每个区域中，单元地电源线Vss是循环形成的。在每个区域区域之外形成焊盘接地电源线Vss'。单元接地电源线Vss和焊盘接地电源线Vss'中的每一个通过并联连接的多个保险丝F连接。

4. 发明授权

US5068831A Data read circuit for semiconductor storage device 失效
标题翻译：半导体存储器件的数据读取电路
公开(公告)号：US5068831A
公开(公告)日：1991-11-26
申请号：US550025
申请日：1990-07-09
申请人： Satoru Hoshi , Masami Masuda , Takayuki Kawaguchi
发明人： Satoru Hoshi , Masami Masuda , Takayuki Kawaguchi
IPC分类号： G11C11/41 , G11C7/06 , G11C7/12 , G11C7/22 , G11C11/409 , G11C11/417 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C7/12 , G11C7/06 , G11C7/22
摘要： In a data read circuit, for a semiconductor storage device, data of a memory cell (11) selected according to an address is inputted to a sense amplifier (22) via a pair of complementary first data lines (N1 to N6). The sense amplifier outputs the inputted and amplified data to a pair of complementary second data lines (N7, N8). First switching means (Tr3) equalizes the pair of complementary first data lines (N5, N6) at the input side of the sense amplifier (22) by making the first data lines conductive with respect to each other. Second switching means (Tr4) equalizes the pair of complementary second data lines (N7, N8) by making the second data lines conductive with respect to each other. Third switching means (Tr5, Tr6) equalizes by making the pair of first data lines (N5, N6) at the input side of the sense amplifier (22) and corresponding ones of the pair of second data lines (N7, N8) conductive with respect to each other. Second equalizing pulse generator means (42) generates a second equalizing pulse (.PHI..sub.eq ') when the address is changed, and turns on the first switch means (Tr3) by applying the second equalizing pulse to a control terminal of the first switch means. First equalizing pulse generator means (41) generates a first equalizing pulse (.PHI..sub.eq) when the address is changed, and turns on the second and third switching means (Tr4, Tr5, Tr6) by applying the second equalizing pulse to gate terminals of the second and third switching means. The load capacitance ]C(.PHI..sub.eq ')] connected to an output terminal of the second equalizing pulse generating means (42) is set smaller than the load capacitance [C(.PHI..sub.eq)] connected to an output terminal of the first equalizing pulse generator means (41). The number of stages of logical circuits constituting the second equalizing pulse generator means (42) is smaller than the number of stages of logical circuits constituting the first equalizing pulse generator means (41). Accordingly, with this data read circuit for a semiconductor storage device, the second equalizing pulse (.PHI..sub.eq ') from the second equalizing pulse generator means (42) is established earlier than the first equalizing pulse (.PHI..sub.eq) from the first equalizing pulse generator means (41).

5. 发明授权

US09802992B2 Cell into which protein, which can serve as polymerization nucleus of protein polymer, or polymer thereof is introduced, and method for production of the cell 有权
公开(公告)号：US09802992B2
公开(公告)日：2017-10-31
申请号：US12086124
申请日：2006-12-06
申请人： Takashi Nonaka , Sayuri Watanabe , Masami Masuda , Masato Hasegawa
发明人： Takashi Nonaka , Sayuri Watanabe , Masami Masuda , Masato Hasegawa
IPC分类号： C12N5/079 , C12N5/0793 , G01N33/50 , C07K14/47 , G01N33/68
CPC分类号： C07K14/47 , C12N5/0619 , C12N5/0622 , C12N2503/02 , C12N2510/00 , G01N33/5058 , G01N33/6896 , G01N2500/10
摘要： The present invention has the object of providing a cell into which a protein, which can serve as a polymerization nucleus of a protein polymer, or polymer thereof is introduced, and a method for producing the cell. The invention relates to a cell into which a protein, which can serve as a polymerization nucleus of a protein polymer, or a polymer thereof is introduced, a method for producing the cell, and a method of screening for a compound inhibiting an intracellular accumulation of a protein containing fibril structures, wherein the method comprises bringing a candidate substance into contact with the cell.

6. 发明申请

US20080285324A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080285324A1
公开(公告)日：2008-11-20
申请号：US11834932
申请日：2007-08-07
申请人： Yukako HATTORI , Katsumi Abe , Masami Masuda , Hiroshi Nakamura
发明人： Yukako HATTORI , Katsumi Abe , Masami Masuda , Hiroshi Nakamura
IPC分类号： G11C5/02
CPC分类号： H01L27/105 , G11C7/1042 , G11C7/18 , H01L27/0207 , H01L27/11898
摘要： Shunt regions are formed at certain intervals in a memory cell array region as extending in a second direction. The shunt regions each include a contact formed to connect a word line or a signal line wired in the same direction to another metal wire. Extension regions are each formed of an extension of the shunt region in the data cache array region. Data input/output lines extend in a first direction and transfer data on bit lines simultaneously via a data cache array. Sense circuits are arranged around the data cache array and connected to the data input/output lines respectively. The data input/output lines are divided at a certain interval in the first direction. The divided portions are connected to respective leads formed in the extension region in the longitudinal direction thereof and connected to the sense circuits via the leads.
摘要翻译：分流区域以沿第二方向延伸的存储单元阵列区域中的特定间隔形成。并联区域各自包括形成为将字线或者以相同方向布线的信号线连接到另一金属线的触点。延伸区域各自由数据高速缓存阵列区域中的分流区域的扩展形成。数据输入/输出线在第一方向上延伸，并通过数据高速缓存阵列同时传送位线上的数据。检测电路被布置在数据高速缓存阵列的周围，分别连接到数据输入/输出线。数据输入/输出线在第一个方向上以一定间隔分开。分开的部分连接到在其延伸区域中形成在其纵向方向上的各个引线，并且经由引线连接到感测电路。

7. 发明授权

US5073872A Data output control circuit for semiconductor storage device 失效
标题翻译：半导体存储器件的数据输出控制电路
公开(公告)号：US5073872A
公开(公告)日：1991-12-17
申请号：US551303
申请日：1990-07-12
申请人： Masami Masuda , Kenichi Nakamura
发明人： Masami Masuda , Kenichi Nakamura
IPC分类号： G11C11/41 , G11C7/10 , G11C11/407 , G11C11/409
CPC分类号： G11C7/1057 , G11C7/1006 , G11C7/1048 , G11C7/1051 , G11C7/106
摘要： An equalizing transistor is connected between first and second data lines to which data corresponding to data stored in a memory cell selected by an address is outputted. When the equalizing pulse is applied to the control terminal of the equalizing transistor, the first and second data lines are made conductive with respect to each other so that the data lines are set at a predetermined equal potential. An output buffer switch has first and second output switches connected in series between a power source supply terminal and ground. An interconnection node between the output switches is a data output terminal. One or the other of the pair of data lines are connected to the control nodes of the first and second output switches. A data line switch is connected between the equalizing transistor and the output buffer switch of at least one of the pair of data lines. The data line switch is turned on and off by the equalizing pulse. A latch is connected between the data switch and the correspondingly connected ones of the output switch at said the lines. The latch latches the potentials at the data lines immediately before the turn-off of the data line switch and applies the latched potentials to the control terminals of the output switch.

8. 发明授权

US4585379A Precision positioning device 失效
标题翻译：精密定位装置
公开(公告)号：US4585379A
公开(公告)日：1986-04-29
申请号：US333632
申请日：1981-12-22
申请人： Kazuhiko Nagayama , Masami Masuda , Yukio Maeda
发明人： Kazuhiko Nagayama , Masami Masuda , Yukio Maeda
IPC分类号： B23D59/00 , B27B5/30 , B28D5/02 , G05B19/23 , B23Q15/00 , G01B9/02
CPC分类号： B28D5/024 , B23D59/002 , B27B5/30 , G05B19/231 , G05B2219/37275 , G05B2219/49169 , Y10T408/175 , Y10T408/6757 , Y10T409/304648 , Y10T409/306832 , Y10T409/308008
摘要： In effecting positioning of a workpiece relative to a working tool, indexing is carried out by obtaining precision measurement of the relative distance between the workpiece and the working tool by using a laser beam. Positioning can be effected with improved precision and working can be achieved with improved dimensional accuracy.
摘要翻译：在实现工件相对于加工工具的定位时，通过使用激光束来获得工件与加工工具之间的相对距离的精确测量来进行分度。可以提高精度进行定位，并且可以在提高尺寸精度的情况下实现加工。

9. 发明授权

US5594281A Semiconductor apparatus having wiring structure of an integrated circuit in which a plurality of logic circuits of the same structure are arranged in the same direction 失效
标题翻译：具有集成电路的布线结构的半导体装置，其中相同结构的多个逻辑电路沿相同的方向布置
公开(公告)号：US5594281A
公开(公告)日：1997-01-14
申请号：US608937
申请日：1996-02-29
申请人： Masami Masuda
发明人： Masami Masuda
IPC分类号： H01L21/82 , G11C11/401 , G11C11/408 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/48 , H01L29/44
CPC分类号： H01L23/5222 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： In a semiconductor apparatus, a first circuit provided on a major surface of a semiconductor substrate. The first circuit includes a plurality of logic circuits of an identical structure, the logic circuits having input terminals supplied with identical signals. First metal wiring is provided on the semiconductor substrate in a direction identical to a direction of arrangement of the logic circuits, the first metal wiring being connected to one of the input terminals of each of the logic circuits. A second circuit provided on the major surface of the semiconductor substrate in an outside area which does not overlap an area extending in a direction perpendicular to the direction of arrangement of the logic circuits, the second circuit supplying an identical signal to the input terminals of the logic circuits of the first circuit. A second metal wiring is connected between an output terminal of the second circuit and a substantially middle point of the first metal wiring. The second metal wiring has a portion situated in parallel to the logic circuits. Thereby, an influence of wiring delay due to a difference in distances among the logic circuits can be reduced and a high-speed operation is achieved.
摘要翻译：在半导体装置中，设置在半导体基板的主表面上的第一电路。第一电路包括具有相同结构的多个逻辑电路，逻辑电路具有被提供相同信号的输入端。第一金属布线沿着与逻辑电路的布置方向相同的方向设置在半导体基板上，第一金属布线连接到每个逻辑电路的输入端之一。第二电路设置在半导体衬底的主表面上的外部区域中，该外部区域不与垂直于逻辑电路的布置方向的方向延伸的区域重叠，第二电路向第二电路的输入端提供相同的信号第一电路的逻辑电路。第二金属布线连接在第二电路的输出端和第一金属布线的大致中点之间。第二金属布线具有与逻辑电路平行的部分。由此，可以降低逻辑电路间的距离差引起的布线延迟的影响，实现高速运转。

10. 发明授权

US5544123A Semiconductor memory device having a test circuit 失效
标题翻译：具有测试电路的半导体存储器件
公开(公告)号：US5544123A
公开(公告)日：1996-08-06
申请号：US395031
申请日：1995-02-27
申请人： Satoru Hoshi , Masami Masuda
发明人： Satoru Hoshi , Masami Masuda
IPC分类号： G01R31/28 , G11C8/10 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , G11C8/00
CPC分类号： G11C29/34 , G11C29/50 , G11C8/10 , G11C11/401
摘要： A plurality of voltage supply circuits each including an inverter circuit are provided at the final stage of a row decoder. The voltage supply circuits are supplied with voltage Vdd and voltage Vxx. The voltage Vxx is set at a level of Vss in a normal operation mode and at a level higher than that of Vdd in a burn-in test mode. In the latter mode, the voltage Vdd is applied to the voltage supply circuit connected to a selected word line, while the voltage Vxx (higher than Vdd) is applied to the voltage supply circuit connected to a nonselected word line. All word lines are therefore set at a high level and rendered in a selective state.
摘要翻译：在行解码器的最后一级设置有包括反相器电路的多个电压供给电路。电压供给电路被供给电压Vdd和电压Vxx。电压Vxx在正常工作模式下设定在Vss的电平，并且在老化测试模式下设定为高于Vdd的电平。在后一种模式中，电压Vdd被施加到连接到所选字线的电压供应电路，而电压Vxx（高于Vdd）被施加到连接到非选择字线的电压供应电路。因此，所有字线被设置在高电平并且呈现在选择状态。

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