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1. 发明授权

US5757303A Multi-bit A/D converter having reduced circuitry 失效
标题翻译：具有减少电路的多位A / D转换器
公开(公告)号：US5757303A
公开(公告)日：1998-05-26
申请号：US649063
申请日：1996-05-16
申请人： Yuichi Nakatani , Satoshi Takahashi , Masami Aiura
发明人： Yuichi Nakatani , Satoshi Takahashi , Masami Aiura
IPC分类号： H03M1/14 , H03M1/20 , H03M1/36
CPC分类号： H03M1/204 , H03M1/365
摘要： The A/D converter comprises a resistor series (30), a plurality of first comparators (1) and a plurality of second comparators (2). Resistor series (30) has a plurality of resistors(R) connected in series between two terminals to which predetermined reference voltages are applied. First comparator (1) compares a node voltage between resistors and an analog voltage signal to be compared. Second comparator (2) compares an average voltage of the two node voltages across each resistor R and the analog voltage signal. First and second comparators (1,2) are disposed alternatively.
摘要翻译： A / D转换器包括电阻器系列（30），多个第一比较器（1）和多个第二比较器（2）。电阻器系列（30）具有串联连接到施加了预定参考电压的两个端子之间的多个电阻器（R）。第一比较器（1）比较电阻器和待比较的模拟电压信号之间的节点电压。第二比较器（2）比较每个电阻器R上的两个节点电压的平均电压和模拟电压信号。第一和第二比较器（1,2）交替布置。

2. 发明授权

US06788234B2 Method of selecting cells for input code in a digital-to-analog converter 失效
标题翻译：在数模转换器中选择输入代码的单元的方法
公开(公告)号：US06788234B2
公开(公告)日：2004-09-07
申请号：US10359503
申请日：2003-02-05
申请人： Masami Aiura , Satoshi Takahashi , Yuichi Nakatani
发明人： Masami Aiura , Satoshi Takahashi , Yuichi Nakatani
IPC分类号： H03M166
CPC分类号： H03M1/0665 , H03M1/747
摘要： A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C01 through C63. A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C02-C62, ranging from the second left-most current source cell C02 to the second right-most current source cell C62, are used as cyclically selected cells. The remaining left-most current source cell C01 and right-most current source cell C63 are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.
摘要翻译：响应于数模转换器的输入代码来选择单元的方法基于选择模式的周期性来分配噪声以减小其值，而不依赖于输入代码。 6位电流输出型数模转换器具有63个电流源单元C01至C63。当前源单元的素数或61个被用作循环选择的单元。也就是说，从第二最左电流源电池C02到第二最右边电流源电池C62的61个电流源电池C02-C62用作循环选择的电池。剩余的最左电流源单元C01和最右边的电流源单元C63用作非循环选择的单元。响应于使用数据加权平均（DWA）技术的输入代码选择周期性选择的单元，包括61个电流源单元。

3. 发明授权

US5977892A Offset cancellation circuit 失效
标题翻译：偏移消除电路
公开(公告)号：US5977892A
公开(公告)日：1999-11-02
申请号：US648645
申请日：1996-05-16
申请人： Yuichi Nakatani , Satoshi Takahashi , Masami Aiura
发明人： Yuichi Nakatani , Satoshi Takahashi , Masami Aiura
IPC分类号： H03K17/16 , H03K17/687 , H03M1/06
CPC分类号： H03K17/162 , H03K17/6872
摘要： An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.
摘要翻译：提供了用于模拟开关（10）的偏移消除电路（1），其大大减少了由模拟开关电路引起的偏移电压。电路（1）包括彼此串联连接的第二P沟道晶体管（2）和第三N沟道晶体管（4），第二P沟道晶体管和第三N沟道晶体管的漏极被连接到输出端子; 连接到第二N沟道晶体管和第三P沟道晶体管的第二N沟道晶体管和第三P沟道晶体管，第二N沟道晶体管和第三P沟道晶体管的漏极连接到输出端; 第二P沟道晶体管的栅极连接到N沟道晶体管的栅极; 并且第二N沟道晶体管的栅极连接到P沟道晶体管的栅极。

4. 发明授权

US06686859B2 Digital-to-analog-converter 失效
标题翻译：数模转换器
公开(公告)号：US06686859B2
公开(公告)日：2004-02-03
申请号：US10351724
申请日：2003-01-27
申请人： Masami Aiura , Satoshi Takahashi , Yuichi Nakatani
发明人： Masami Aiura , Satoshi Takahashi , Yuichi Nakatani
IPC分类号： H03M166
CPC分类号： H03M1/0643 , H03M1/0682 , H03M1/747
摘要： It is an objective to provide a digital-to-analog converter circuit that allows the value of the current output from each current source cell to be identical, regardless of the position of that current source cell relative to the power supply line. To ensure that the voltages supplied to the respective current source cells are identical, the power supply lines La and Lb are disposed in the form of a right triangle modified such that their line widths W1 and W2 become constantly narrower on one side depending on the position at which the power supply lines La and Lb are formed. The power supply lines La and Lb are also disposed such that their hypotenuses are opposite to each other.
摘要翻译：目的是提供数模转换器电路，其允许来自每个电流源单元的电流输出的值相同，而不管该电流源单元相对于电源线的位置如何。为了确保提供给各个电流源单元的电压相同，电源线La和Lb以直角三角形的形式被设置，使得它们的线宽W1和W2根据位置在一侧变得不断变窄在其上形成电源线La和Lb。电源线La和Lb也被布置成使得它们的斜边彼此相对。

5. 发明授权

US06346901B1 Digital-to-analog conversion circuit 失效
标题翻译：数模转换电路
公开(公告)号：US06346901B1
公开(公告)日：2002-02-12
申请号：US09470121
申请日：1999-12-22
申请人： Masami Aiura , Yuichi Nakatani , Takashi Kumazaki
发明人： Masami Aiura , Yuichi Nakatani , Takashi Kumazaki
IPC分类号： H03M180
CPC分类号： H03M1/0678 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.
摘要翻译：一种数模转换电路，包括以矩阵排列的多个单位电流输出单元（1）。每个电流输出单元（1）包括具有电源输入和电流输出的单元电流源（11）和连接到电流输出并具有两个开关输出端子的选择开关（12）。电路还包括设置在矩阵中的行上的至少一个1/2和/或1/4加权电流输出单元（2），以及设置在期望行上的至少一个½和/或¼个辅助电流源（8），使得单位的总电流消耗量，每一行的加权和补充电流源基本相同。解码器响应于数字信号，随着数字信号逐渐增加，一个接一个地控制选择开关的切换。

6. 发明申请

US20060215900A1 Image correction method 有权
公开(公告)号：US20060215900A1
公开(公告)日：2006-09-28
申请号：US11360584
申请日：2006-02-24
申请人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
发明人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
IPC分类号： G06K9/00
CPC分类号： G06K9/748 , G06K9/03
摘要： An image correction method having a small number of setting parameters achieved by integrating shift (alignment) in unit of a sub-pixel and image correction. A relationship between an inspection reference pattern image and a pattern image under test is identified, a mathematical expression model which fits a pixel error, expansion and contraction/distortion noise, and sensing noise of the image is constructed, and the model is simulated to generate an estimation model image.

7. 发明授权

US4745393A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4745393A
公开(公告)日：1988-05-17
申请号：US911154
申请日：1986-09-24
申请人： Toshiro Tsukada , Seiichi Ueda , Tatsuji Matsuura , Yuichi Nakatani , Eiki Imaizumi
发明人： Toshiro Tsukada , Seiichi Ueda , Tatsuji Matsuura , Yuichi Nakatani , Eiki Imaizumi
IPC分类号： H03M1/00 , H03M1/36
CPC分类号： H03M1/147
摘要： In a serial-parallel A/D converter, at least two sets of comparators are provided for the conversion of the low-order bits and are operated in a cyclic fashion. Since the subsequent input can be subjected to the A/D conversion without waiting for the determination of the low-order bits, the conversion speed is increased.
摘要翻译：在串行并行A / D转换器中，提供至少两组比较器用于低位位的转换，并以循环方式操作。由于随后的输入可以进行A / D转换而不等待确定低位，所以转换速度增加。

8. 发明授权

US07627165B2 Pattern inspection method and apparatus using linear predictive model-based image correction technique 有权
标题翻译：使用基于线性预测模型的图像校正技术的图案检查方法和装置
公开(公告)号：US07627165B2
公开(公告)日：2009-12-01
申请号：US11360813
申请日：2006-02-24
申请人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
发明人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
IPC分类号： G06K9/00
CPC分类号： G03F7/7065 , G03F1/84 , G03F7/705 , G06T7/0004
摘要： An image correction device for use in pattern inspection apparatus is disclosed. This device includes a pattern extraction unit for extracting a pattern, as a cut-and-paste pattern, from a pattern existence region of an inspection reference pattern image and a pattern image of a workpiece being tested. The device also includes a pattern pasting unit for pasting the cut-and-paste pattern in blank regions of the reference and under-test pattern images to thereby create a pasted reference pattern image and a pasted test pattern image. The device further includes an equation generator for generating by linear predictive modeling a set of simultaneous equations relative to the pasted reference and test pattern images, a parameter generator for solving these equations to obtain a model parameter(s), and a unit for creating a corrected pattern image by the linear predictive modeling using the model parameter(s).
摘要翻译：公开了一种用于图案检查装置的图像校正装置。该装置包括：图案提取单元，用于从检查参考图案图像的图案存在区域和被测工件的图案图像中提取图案作为切割和粘贴图案。该装置还包括一个图案粘贴单元，用于将剪切和粘贴图案粘贴在参考和未测试图案图像的空白区域中，从而产生粘贴的参考图案图像和粘贴的测试图案图像。该装置还包括一个等式发生器，用于通过线性预测建模生成相对于粘贴的参考和测试图案图像的一组联立方程，用于求解这些方程以获得模型参数的参数发生器，以及用于创建通过使用模型参数的线性预测建模来校正图案图像。

9. 发明授权

US06233354B1 Character recognition device 有权
标题翻译：字符识别装置
公开(公告)号：US06233354B1
公开(公告)日：2001-05-15
申请号：US09272312
申请日：1999-03-19
申请人： Yuichi Nakatani
发明人： Yuichi Nakatani
IPC分类号： G06K900
CPC分类号： G06K9/03 , G06K9/32 , G06K2209/01
摘要： The key character selection means selects a character candidate as a standard when evaluating the size information of the extracted area of other character candidates. The doubtful character selection means evaluates size information of the extracted areas of other character candidates making the size information of the extracted area of the key character the standard, and selects the character candidate having deviated size information as a doubtful character. The character reconfirmation means makes the size information of the extracted area of the key character the standard and infers the size information of the extracted area of the relevant character candidate for each character candidate selected by the doubtful character selection means, and carried out extraction of the relevant character candidate by the input word image based on this size information, and carries out character recognition by matching the external frame of the extracted area with the character frames of the template of the character recognition dictionary.
摘要翻译：关键字选择装置在评价其他字符候补的提取区域的大小信息时，选择候选字符作为标准。可疑字符选择装置评估其他字符候选的提取区域的大小信息，使得提取出的关键字符的区域的尺寸信息成为标准，并且选择具有偏差大小信息的字符候选作为可疑字符。字符再确认装置使得关键字提取区域的尺寸信息成为标准，并且推测由可疑字符选择装置选择的每个字符候选者的相关字符候选者的提取区域的大小信息，并且执行提取通过基于该尺寸信息的输入字图像的相关字符候选，并且通过将提取区域的外部帧与字符识别字典的模板的字符帧进行匹配来执行字符识别。

10. 发明授权

US07539350B2 Image correction method 有权
标题翻译：图像校正方法
公开(公告)号：US07539350B2
公开(公告)日：2009-05-26
申请号：US11360584
申请日：2006-02-24
申请人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
发明人： Junji Oaki , Shinji Sugihara , Yuichi Nakatani
IPC分类号： G06K9/40
CPC分类号： G06K9/748 , G06K9/03
摘要： An image correction method having a small number of setting parameters achieved by integrating shift (alignment) in unit of a sub-pixel and image correction. A relationship between an inspection reference pattern image and a pattern image under test is identified, a mathematical expression model which fits a pixel error, expansion and contraction/distortion noise, and sensing noise of the image is constructed, and the model is simulated to generate an estimation model image.
摘要翻译：一种通过以子像素为单位整合移位（对齐）和图像校正而实现的少量设定参数的图像校正方法。识别检查参考图案图像和被测图案图像之间的关系，构建适合像素误差，扩张和收缩/失真噪声以及图像感测噪声的数学表达式模型，并且模拟模型以产生估计模型图像。

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