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1. 发明授权

US08709896B2 Semiconductor device and fabrication method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08709896B2
公开(公告)日：2014-04-29
申请号：US13440506
申请日：2012-04-05
申请人： Masaki Haneda , Yuka Kase , Masanori Terahara , Takayuki Aoyama
发明人： Masaki Haneda , Yuka Kase , Masanori Terahara , Takayuki Aoyama
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.
摘要翻译：半导体器件包括：半导体衬底，包括具有由器件隔离区限定的第一导电类型的阱，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，并且包括第一侧表面和第二侧表面在第一侧表面上形成的第一侧壁绝缘膜和形成在第二侧表面上的第二侧壁绝缘膜。

2. 发明申请

US20120256264A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20120256264A1
公开(公告)日：2012-10-11
申请号：US13440506
申请日：2012-04-05
申请人： Masaki Haneda , Yuka Kase , Masanori Terahara , Takayuki Aoyama
发明人： Masaki Haneda , Yuka Kase , Masanori Terahara , Takayuki Aoyama
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/78 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.
摘要翻译：半导体器件包括：半导体衬底，包括具有由器件隔离区限定的第一导电类型的阱，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，并且包括第一侧表面和第二侧表面在第一侧表面上形成的第一侧壁绝缘膜和形成在第二侧表面上的第二侧壁绝缘膜。

3. 发明授权

US08039358B2 Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted 有权
标题翻译：制造其上安装有多种类型的晶体管的半导体器件的方法
公开(公告)号：US08039358B2
公开(公告)日：2011-10-18
申请号：US12053089
申请日：2008-03-21
申请人： Masanori Terahara , Masaki Nakagawa
发明人： Masanori Terahara , Masaki Nakagawa
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823814 , H01L21/823857 , H01L21/823878
摘要： A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
摘要翻译：制造半导体器件的方法包括以下步骤：在半导体衬底上形成沟槽以限定第一和第二元件区域; 在沟槽中埋设第一氧化膜; 在所述第一和第二元件区域的表面上形成第二氧化物膜; 使用第一掩模进行第一离子掺杂，所述第一掩模暴露含有所述第一元素区域的第一区域和所述第一氧化物的一部分; 使用暴露含有第二元素区域的第二区域和第一氧化物膜的一部分的第二掩模进行第二离子掺杂; 以及通过蚀刻去除在第一元件区域和第二元件区域中形成的第二氧化物膜，并且在执行第一或第二离子掺杂之后，使用第一或第二掩模来选择性地减薄第一氧化物膜。

4. 发明申请

US20100144117A1 Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method 有权
标题翻译：具有通过有源区域的表面变形而改善了器件特性的半导体器件及其制造方法
公开(公告)号：US20100144117A1
公开(公告)日：2010-06-10
申请号：US12708519
申请日：2010-02-18
申请人： Sadahiro Kishii , Hirofumi Watatani , Masanori Terahara , Ryo Tanabe , Kaina Suzuki , Shigeo Satoh
发明人： Sadahiro Kishii , Hirofumi Watatani , Masanori Terahara , Ryo Tanabe , Kaina Suzuki , Shigeo Satoh
IPC分类号： H01L21/762
CPC分类号： H01L29/045 , H01L21/76232 , H01L29/7846
摘要： A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.
摘要翻译：沟槽形成在半导体衬底的表面层中，沟槽围绕有源区。在半导体器件上沉积由绝缘材料制成的下绝缘膜，下绝缘膜填充沟槽的下部区域并在上部区域留下空的空间。在其上具有拉伸应力的由绝缘材料制成的上绝缘膜沉积在下绝缘膜上，上绝缘膜填充留在上部空间中的空白空间。去除沉积在半导体衬底上而不是在沟槽中的上绝缘膜和下绝缘膜。

5. 发明申请

US20090197355A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM 有权
标题翻译：制造半导体器件和半导体器件制造系统的方法
公开(公告)号：US20090197355A1
公开(公告)日：2009-08-06
申请号：US12364830
申请日：2009-02-03
申请人： Masanori Terahara
发明人： Masanori Terahara
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/12 , H01L21/76224
摘要： A method for manufacturing a semiconductor device that controls the influence of a thickness of a stopper film even if there is a change in the thickness of the stopper film by measuring the thickness prior to etching to a predetermined thickness.
摘要翻译：即使通过测量蚀刻前的厚度达到预定厚度，即使阻挡膜的厚度发生变化，也可以控制阻挡膜厚度的影响的半导体器件的制造方法。

6. 发明申请

US20120009752A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120009752A1
公开(公告)日：2012-01-12
申请号：US13238336
申请日：2011-09-21
申请人： Takayuki Wada , Masanori Terahara , Junji Oh
发明人： Takayuki Wada , Masanori Terahara , Junji Oh
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.
摘要翻译：一种制造半导体器件的方法包括：形成具有第一表面和第二表面的硅衬底，所述硅衬底不包括氧化膜或厚度不大于100nm的氧化物膜，至少在第二表面上形成第一氧化膜所述硅衬底通过至少覆盖所述第一表面形成第一膜，通过使所述第一膜图案化而在所述第一表面上形成掩模图案，通过使用所述掩模图案作为掩模在所述第一表面上形成器件分离区域，形成在所述第一表面上形成栅极绝缘膜，经由所述栅极绝缘膜在所述第一表面上形成栅电极，在所述栅电极的每一侧上形成源极和漏极，以及在所述硅衬底上形成布线层，同时保持所述第一氧化膜在第二表面上。

7. 发明申请

US20060281245A1 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US20060281245A1
公开(公告)日：2006-12-14
申请号：US11358317
申请日：2006-02-22
申请人： Masaki Okuno , Sadahiro Kishii , Hiroshi Morioka , Masanori Terahara , Shigeo Satoh , Kaina Suzuki
发明人： Masaki Okuno , Sadahiro Kishii , Hiroshi Morioka , Masanori Terahara , Shigeo Satoh , Kaina Suzuki
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/76235 , H01L21/823878
摘要： A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

8. 发明授权

US06979610B2 Semiconductor device fabrication method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US06979610B2
公开(公告)日：2005-12-27
申请号：US10694984
申请日：2003-10-29
申请人： Masanori Terahara , Hiroshi Morioka
发明人： Masanori Terahara , Hiroshi Morioka
IPC分类号： H01L21/3065 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823481 , H01L21/76229
摘要： The semiconductor device fabrication method comprises the step of forming a first insulation film 14 over a semiconductor substrate 10; the step of forming a semiconductor film 16 over the first insulation film 14; the step of forming a resist film 20 over the semiconductor film 16; the step of forming openings 21 in the resist film 20; the step of etching the semiconductor film 16 with the resist film 20 as the mask; the step of etching the first insulation film 14 with the semiconductor film 16 as the mask; and the step of etching the semiconductor substrate 10 with the first insulation film 14 as the mask to form trenches 22 in the semiconductor substrate 10. Silicon nitride film is patterned, using a mask of polysilicon film, whereby the silicon nitride film can be etched with high selectivity to the polysilicon film. Accordingly, a good pattern of the silicon nitride film can be formed. Even when micronized trenches are formed in a semiconductor substrate with silicon nitride film as a mask, the trenches can be formed in a required configuration. Thus, good element isolation regions can be formed, further micronized.
摘要翻译：半导体器件制造方法包括在半导体衬底10上形成第一绝缘膜14的步骤; 在第一绝缘膜14上形成半导体膜16的步骤; 在半导体膜16上形成抗蚀剂膜20的步骤; 在抗蚀剂膜20中形成开口21的步骤; 用抗蚀剂膜20作为掩模蚀刻半导体膜16的步骤; 用半导体膜16作为掩模蚀刻第一绝缘膜14的步骤; 以及利用第一绝缘膜14作为掩模蚀刻半导体衬底10的步骤，以在半导体衬底10中形成沟槽22.使用多晶硅膜的掩模对氮化硅膜进行构图，从而可以用氮化硅膜蚀刻氮化硅膜对多晶硅膜的选择性高。因此，可以形成氮化硅膜的良好图案。即使在用氮化硅膜作为掩模的半导体衬底中形成微粉化的沟槽，也可以形成所需的构造。因此，可以形成良好的元件隔离区域，进一步微粉化。

9. 发明授权

US08273630B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08273630B2
公开(公告)日：2012-09-25
申请号：US13238336
申请日：2011-09-21
申请人： Takayuki Wada , Masanori Terahara , Junji Oh
发明人： Takayuki Wada , Masanori Terahara , Junji Oh
IPC分类号： H01L21/761
CPC分类号： H01L21/76224 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.
摘要翻译：一种制造半导体器件的方法包括：形成具有第一表面和第二表面的硅衬底，所述硅衬底不包括氧化膜或厚度不大于100nm的氧化物膜，至少在第二表面上形成第一氧化膜所述硅衬底通过至少覆盖所述第一表面形成第一膜，通过使所述第一膜图案化而在所述第一表面上形成掩模图案，通过使用所述掩模图案作为掩模在所述第一表面上形成器件分离区域，形成在所述第一表面上形成栅极绝缘膜，经由所述栅极绝缘膜在所述第一表面上形成栅电极，在所述栅电极的每一侧上形成源极和漏极，以及在所述硅衬底上形成布线层，同时保持所述第一氧化膜在第二表面上。

10. 发明授权

US08193048B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08193048B2
公开(公告)日：2012-06-05
申请号：US12061367
申请日：2008-04-02
申请人： Masato Miyamoto , Masanori Terahara
发明人： Masato Miyamoto , Masanori Terahara
IPC分类号： H01L21/8238
CPC分类号： H01L21/76232
摘要： A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.
摘要翻译：半导体器件形成在半导体衬底中，其中半导体衬底具有用于彼此隔离元件的沟槽，沟槽在其底部具有不均匀性，并且绝缘体被埋在沟槽中。

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