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1. 发明授权

US06807082B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06807082B2
公开(公告)日：2004-10-19
申请号：US10282013
申请日：2002-10-29
申请人： Masaki Aoki , Keizo Morita
发明人： Masaki Aoki , Keizo Morita
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A stacked FeRAM uses a structure where the bit line is formed above the ferroelectric capacitor. The word line is formed so that it moves away from the opposing other word line in areas near the contact plug with the relevant contact plug in between, and moves toward the other word line in areas not near the contact plug, and the contact hole is formed so that it is displaced alternately with respect to the longitudinal centerline of the relevant plate line.
摘要翻译：堆叠的FeRAM使用在铁电电容器上方形成位线的结构。字线被形成为使得其在与接触插塞附近的区域中相对的另一个字线移动，并且相对于接触插头在其之间移动，并且接触孔是形成为相对于相关板线的纵向中心线交替排列。

2. 发明授权

US07525846B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07525846B2
公开(公告)日：2009-04-28
申请号：US11485553
申请日：2006-07-13
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/03
CPC分类号： G11C11/22
摘要： A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.
摘要翻译：一种存储器件，包括具有根据数据逻辑累积电荷的电容器的存储单元，连接到存储单元的位线，用于将位线中的电荷传送到输出节点的电荷转移电路，连接到位线的虚拟存储单元，以及用于根据位线的电压变化来控制电荷转移电路的电荷转移能力的控制电路。

3. 发明申请

US20070217250A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20070217250A1
公开(公告)日：2007-09-20
申请号：US11485553
申请日：2006-07-13
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： There is provided a memory device including a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.
摘要翻译：提供了一种存储器件，其包括具有根据数据逻辑累积电荷的电容器的存储单元，连接到存储单元的位线，用于将位线中的电荷转移到输出的电荷转移电路节点，连接到位线的虚拟存储单元，以及控制电路，用于根据位线电压的变化来控制电荷转移电路的电荷转移能力。

4. 发明授权

US08064241B2 Semiconductor memory including voltage detection circuit for generating sense amplifier signal 有权
标题翻译：半导体存储器包括用于产生读出放大器信号的电压检测电路
公开(公告)号：US08064241B2
公开(公告)日：2011-11-22
申请号：US12603065
申请日：2009-10-21
申请人： Keizo Morita , Kenichi Nakabayashi
发明人： Keizo Morita , Kenichi Nakabayashi
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/08 , G11C7/222 , G11C7/227
摘要： A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.
摘要翻译：当对一对位线之一读取的电荷量达到预定量时，电压检测电路输出检测信号。定时发生器的屏蔽电路屏蔽感测放大器激活信号的输出，直到输出检测信号。读出放大器与读出放大器激活信号同步地确定从存储器单元读取到位线的数据的逻辑。在从存储器单元读取预定量的电荷到位线之后，即在检测信号被输出之后，开始读出放大器的操作。因此，即使由于半导体存储器的制造条件的变化而导致定时信号的输出定时变得早，因此可以在读出放大器中正确地锁存从存储单元读出的数据。结果，可以防止半导体存储器的故障。

5. 发明授权

US07729181B2 Semiconductor storage device using a bitline GND sensing scheme for a reduced real estate of pre-sense amplifier 有权
标题翻译：半导体存储设备使用位线GND感测方案，用于预读取放大器的减少的空间
公开(公告)号：US07729181B2
公开(公告)日：2010-06-01
申请号：US11653909
申请日：2007-01-17
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C7/06
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.
摘要翻译：半导体存储装置包括连接到板线和位线的存储单元，连接到位线的电位移动电路在施加电压时临时改变与位线的电压变化相对应的输出电压用于传送与电位移动电路的临时输出电压变化相对应的存储在电位移位电路上的电荷的电荷转移电路，以及用于在累积转移电荷之后从存储单元产生读取电压的电荷累积电路。

6. 发明授权

US4319188A Magnetic rotary encoder for detection of incremental angular displacement 失效
标题翻译：用于检测增量角位移的磁性旋转编码器
公开(公告)号：US4319188A
公开(公告)日：1982-03-09
申请号：US219759
申请日：1980-12-24
申请人： Susumu Ito , Morimasa Nagao , Kaoru Toki , Keizo Morita
发明人： Susumu Ito , Morimasa Nagao , Kaoru Toki , Keizo Morita
IPC分类号： G01B7/00 , G01B7/30 , G01D5/14 , G01D5/16 , G01D5/244 , G01D5/245 , G01P3/487 , H03M1/00 , G01P3/48
CPC分类号： G01D5/145 , G01D5/24404 , G01D5/2457 , G01P3/487 , H03M1/30
摘要： A magnetic rotary encoder for detecting incremental angular displacement, angular velocity and rotating direction using magneto-resistors is disclosed. A drum, disk or cupshaped rotary member is attachable to a rotatable shaft. A magnetic medium is provided on a surface of the rotary member and is divided at a pitch p into a plurality of magnetic sections each of which has a magnetic signal recorded. The magnetic medium produces an alternating magnetic field as the rotary member revolves. Alternatively, a plurality of permanent magnets are provided on the surface of the rotary member to produce the alternating magnetic field of the rotary member revolves. A magnetic field detector includes at least one magneto-resistor having a stripe-like configuration with width D. The magneto-resistor is located in the vicinity of the rotary member so as to be spaced from the magnetic medium or the permanent magnets by equal to or less than p at its nearest portion and by equal to or less than 20p at its furthest portion. The width D is selected so as not to be in excess of 20p but to be equal or less than p .sec .phi., where .phi. is an angle defined by the nearest surfaces of the magneto-resistor and the magnetic medium or permanent magnets. The magneto-resistor is responsive to the alternating magnetic field to generate an analog signal representative of its electrical resistance change corresponding to the increment of the rotational angle of the rotary member. A rotary condition detector is electrically connected to the magnetic field detector to receive the analog signal and produce signals indicative of the rotating conditions of the rotatable shaft.
摘要翻译：公开了一种用于使用磁阻电阻检测增量角位移，角速度和旋转方向的磁旋转编码器。鼓，盘或杯形旋转构件可附接到可旋转的轴。磁性介质设置在旋转构件的表面上，并以间距p分成多个磁区，每个磁区具有记录的磁信号。当旋转构件旋转时，磁介质产生交变磁场。或者，在旋转构件的表面上设置多个永磁体，以产生旋转构件的交变磁场旋转。磁场检测器包括至少一个具有宽度为D的条状结构的磁阻电阻器。磁电阻器位于旋转部件附近，以便与磁介质或永磁体间隔相等或小于其最近部分处的p，并且在其最远部分等于或小于20p。宽度D被选择为不超过20p但是等于或小于p.sec phi，其中phi是由磁电阻器和磁介质或永磁体的最近表面限定的角度。磁阻电阻响应于交变磁场以产生代表其电阻变化的模拟信号，其对应于旋转构件的旋转角度的增量。旋转状态检测器电连接到磁场检测器以接收模拟信号并产生指示可旋转轴的旋转状态的信号。

7. 发明申请

US20090168577A1 SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD 审中-公开
标题翻译：半导体存储器件和数据读取方法
公开(公告)号：US20090168577A1
公开(公告)日：2009-07-02
申请号：US12398816
申请日：2009-03-05
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C7/02
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.
摘要翻译：半导体存储装置包括连接到板线和位线的存储单元，连接到位线的电位移动电路在施加电压时临时改变与位线的电压变化相对应的输出电压然后在对板线施加电压之前输出电压;电荷转移电路，用于转移与电位移动电路的临时输出电压变化对应的电位移位电路上存储的电荷，以及电荷累积电路，用于在累积传送的电荷之后从存储单元产生读取电压。

8. 发明授权

US07180766B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07180766B2
公开(公告)日：2007-02-20
申请号：US11154797
申请日：2005-06-17
申请人： Keizo Morita
发明人： Keizo Morita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.
摘要翻译：半导体存储器具有字线; 各存储电容器的正常存储单元; 正常位线连接到正常存储器单元; 参考存储单元，具有存储规定数据的电容器; 以及连接到参考存储单元的参考位线。当选择字线时，正常位线和参考位线的电位根据存储电容器和参考电容器上的电荷而改变。还提供了电流镜电路，其具有连接到参考位线的第一晶体管漏极和分别连接到通常位线的第二晶体管漏极，第一和第二晶体管的栅极共同连接到参考位线。因此，即使铁电电容器的电容值散布，也可以防止在读取操作期间位线电位的散射。

9. 发明申请

US20060146625A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060146625A1
公开(公告)日：2006-07-06
申请号：US11154797
申请日：2005-06-17
申请人： Keizo Morita
发明人： Keizo Morita
IPC分类号： G11C7/02 , G11C7/14 , G11C11/22
CPC分类号： G11C11/22
摘要： The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.
摘要翻译：半导体存储器具有字线; 各存储电容器的正常存储单元; 正常位线连接到正常存储器单元; 参考存储单元，具有存储规定数据的电容器; 以及连接到参考存储单元的参考位线。当选择字线时，正常位线和参考位线的电位根据存储电容器和参考电容器上的电荷而改变。还提供了电流镜电路，其具有连接到参考位线的第一晶体管漏极和分别连接到通常位线的第二晶体管漏极，第一和第二晶体管的栅极共同连接到参考位线。因此，即使铁电电容器的电容值散布，也可以防止在读取操作期间位线电位的散射。

10. 发明授权

US06659845B2 Grinding method, electronic component, and variable capacitor 有权
标题翻译：研磨方法，电子部件和可变电容器
公开(公告)号：US06659845B2
公开(公告)日：2003-12-09
申请号：US09759587
申请日：2001-01-12
申请人： Hiromichi Takeda , Hiroyuki Kishishita , Hidetoshi Kita , Keizo Morita
发明人： Hiromichi Takeda , Hiroyuki Kishishita , Hidetoshi Kita , Keizo Morita
IPC分类号： B24B100
CPC分类号： B24B1/00 , B24B7/228 , H01G5/06
摘要： A grinding method, in which the grinding operation is performed on a plurality of workpieces having different thicknesses with an end surface in the thickness direction of each workpiece being a surface to be ground, includes the steps of holding the workpieces with a holder such that the surfaces to be ground of the individual workpieces are aligned in the same plane, and grinding the surfaces to be ground of the workpieces while the workpieces are held by the holder. An electronic component provided with an element ground by the grinding method, and a variable capacitor provided with an element ground by the grinding method are also disclosed.
摘要翻译：对具有不同厚度的多个工件进行研磨操作的研磨方法，其中每个工件的厚度方向上的端面是要被研磨的表面，包括以下步骤：用保持器保持工件，使得待研磨的各个工件的表面在同一平面上对准，并且在工件被保持器保持时，研磨待研磨的工件的表面。还公开了一种通过研磨方法设置有元件研磨的电子部件，以及通过研磨方法设置有元件研磨的可变电容器。

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