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1. 发明授权

US5606183A Double-gated turn-off thyristor 失效
标题翻译：双门控关断晶闸管
公开(公告)号：US5606183A
公开(公告)日：1997-02-25
申请号：US352956
申请日：1994-12-09
申请人： Masahito Otsuki , Katsunori Ueno
发明人： Masahito Otsuki , Katsunori Ueno
IPC分类号： H01L29/739 , H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/749 , H01L29/7395 , H01L29/745
摘要： A semiconductor device having a thyristor structure including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type; a first MISFET capable of injecting majority carriers from the fourth semiconductor region into the second semiconductor region; and a second MISFET capable of being turned on and off independently of the first MISFET and extracting majority carriers from the third semiconductor region into the fourth semiconductor region, wherein the fourth semiconductor region is divided into the source region of the first MISFET and the source region of the second MISFET, the latter being formed in a portion isolated from the former, characterized in that the depth of the source region of the second MISFET is different from that of the drain region thereof.
摘要翻译：一种具有晶闸管结构的半导体器件，包括第一导电类型的第一半导体区域，第二导电类型的第二半导体区域，第一导电类型的第三半导体区域和第二导电类型的第四半导体区域; 能够将多数载流子从第四半导体区域注入第二半导体区域的第一MISFET; 以及第二MISFET，其能够独立于所述第一MISFET而导通和截止，并且将多数载流子从所述第三半导体区域提取到所述第四半导体区域中，其中所述第四半导体区域被划分为所述第一MISFET的源极区域和所述源极区域第二MISFET的后部形成在与前者隔离的部分中，其特征在于，第二MISFET的源极区域的深度与漏极区域的深度不同。

2. 发明授权

US5378903A Semiconductor device with low on-voltage and large controllable turn-off current 失效
标题翻译：具有低导通电压和大的可控关断电流的半导体器件
公开(公告)号：US5378903A
公开(公告)日：1995-01-03
申请号：US215777
申请日：1994-03-22
申请人： Masahito Otsuki , Katsunori Ueno
发明人： Masahito Otsuki , Katsunori Ueno
IPC分类号： H01L29/74 , H01L27/04 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H03K17/56 , H01L27/02
CPC分类号： H01L29/7395 , H01L29/7455
摘要： The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.
摘要翻译：半导体器件由EST部分和IGBT部分形成，其中EST部分具有第一MOSFET和第二MOSFET同步开关，并且IGBT部分具有可独立于其控制的第三MOSFET。在半导体器件的关断时，当保持第三MOSFET处于导通状态时关断第一和第二MOSFET并保持IGBT操作。因此，即使由于发射极区域中的结而使势垒的恢复迟到，并且抑制对发射极区域的电荷积累，趋向于流向发射极区域的电流路径朝向发射极电极侧变化。在势垒恢复之后，第三个MOSFET关闭。可放大关断电流可以放大，可以缩短关断时间。

3. 发明授权

US5714774A Two-gate semiconductor power switching device 失效
标题翻译：双栅功率半导体开关器件
公开(公告)号：US5714774A
公开(公告)日：1998-02-03
申请号：US218200
申请日：1994-03-28
申请人： Masahito Otsuki , Katsunori Ueno
发明人： Masahito Otsuki , Katsunori Ueno
IPC分类号： H01L29/74 , H01L27/04 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H03K17/56 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7395
摘要： In a semiconductor device, in addition to a first emitter layer, a second emitter layer is formed on the surface side of a p-type base in spaced-apart relation with the first emitter layer. The first emitter layer is the source region of a first MOSFET, while the second emitter layer is the source region of a second MOSFET. Through signals imparted to first and second gate electrodes, the device, when turned on, operates with a low on-state voltage drop in a thyristor state and, when turned off, undergoes a turn-off in a short time by changing to a transistor state. The main current in the transistor state flows by being offset toward the first emitter layer side with respect to a main-current path on the lower side of the second emitter layer in the thyristor state. Since the current paths in each mode are separated, it is possible to reduce the resistance in the current path in the transistor state without increasing the on-voltage, thereby making it possible to obtain a large latch-up withstand capability.
摘要翻译：在半导体器件中，除了第一发射极层之外，在与第一发射极层间隔开的p型基底的表面侧上形成第二发射极层。第一发射极层是第一MOSFET的源极区，而第二发射极层是第二MOSFET的源极区。通过施加到第一和第二栅电极的信号，器件在导通时以晶闸管状态的低导通状态电压降工作，并且当关断时，通过改变为晶体管在短时间内经历关断州。晶体管状态中的主电流通过在晶闸管状态下相对于第二发射极层的下侧的主电流路径朝向第一发射极侧偏移而流动。由于每个模式中的电流路径是分离的，所以可以在不增加导通电压的情况下减小晶体管状态中的电流路径中的电阻，从而可以获得大的闩锁耐受能力。

4. 发明授权

US5397905A Power semiconductor device having an insulated gate field effect transistor and a bipolar transistor 失效
标题翻译：具有绝缘栅场效应晶体管和双极晶体管的功率半导体器件
公开(公告)号：US5397905A
公开(公告)日：1995-03-14
申请号：US196835
申请日：1994-02-15
申请人： Masahito Otsuki , Katsunori Ueno
发明人： Masahito Otsuki , Katsunori Ueno
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/739 , H01L29/745 , H01L29/78 , H01L29/74 , H01L27/02
CPC分类号： H01L29/1095 , H01L29/7395 , H01L29/7455
摘要： In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.
摘要翻译：在具有绝缘栅场效应晶体管和双极晶体管的半导体器件中，具有比第一导电类型的第二层高的杂质浓度的第一导电类型的掩埋层设置在第二层之间的至少下部区域中第二导电类型的第三层和第二导电类型的第二层之间的边界附近，该第二导电类型的第二层用作场效应晶体管的背栅极和双极晶体管的基极层，以及第二导电类型的第一层。

5. 发明授权

US5894139A Semiconductor device structure for insulated gate bipolar transistor 失效
标题翻译：绝缘栅双极晶体管的半导体器件结构
公开(公告)号：US5894139A
公开(公告)日：1999-04-13
申请号：US864290
申请日：1997-05-28
申请人： Masahito Otsuki , Ryu Saito , Yasuhiko Onishi
发明人： Masahito Otsuki , Ryu Saito , Yasuhiko Onishi
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7395 , H01L29/0696 , H01L29/1095
摘要： A semiconductor device is provided which includes a first-conductivity-type collector layer having a rear surface on which a collector electrode is formed, a second-conductivity-type buffer layer laminated on the collector layer, a second-conductivity-type conductivity modulation layer formed on the buffer layer, a first-conductivity-type emitter layer formed as a well in a surface of the conductivity modulation layer, a second-conductivity-type source region formed in a surface of a well edge portion of the emitter layer, a gate electrode formed through a gate insulating film to overlap the source region and the conductivity modulation layer, and an emitter electrode that is in ohmic contact with both the emitter layer and the source region. In the present device, the second-conductivity-type source region includes a second-conductivity-type source region formed in the well edge of the emitter layer, and a second-conductivity-type source contact region formed adjacent to the source region and held in ohmic contact with the emitter electrode. This source contact region has a higher impurity concentration than the source region.
摘要翻译：提供了一种半导体器件，其包括具有形成有集电极的后表面的第一导电型集电体层，层叠在集电极层上的第二导电型缓冲层，第二导电型导电性调制层形成在缓冲层上的第一导电型发射极层，形成在导电性调制层的表面中的第一导电型发射极层，形成在发射极层的阱边缘部分的表面中的第二导电型源极区域，栅极电极通过栅极绝缘膜形成以与源极区域和导电性调制层重叠，以及与发射极层和源极区域欧姆接触的发射极。在本装置中，第二导电型源极区域包括形成在发射极层的阱边缘中的第二导电型源极区域和与源极区域相邻形成并保持的第二导电型源极接触区域与发射极电极欧姆接触。该源极接触区域具有比源极区域更高的杂质浓度。

6. 发明授权

US5559347A Insulated gate-type bipolar transistor 失效
标题翻译：绝缘栅型双极晶体管
公开(公告)号：US5559347A
公开(公告)日：1996-09-24
申请号：US397418
申请日：1995-03-01
申请人： Tomoyuki Yamazaki , Masahito Otsuki
发明人： Tomoyuki Yamazaki , Masahito Otsuki
IPC分类号： H01L29/78 , H01L27/02 , H01L27/04 , H01L29/739 , H01L29/74 , H01L29/76
CPC分类号： H01L29/7395 , H01L27/0248
摘要： An insulated gate-type bipolar transistor with an overcurrent limiting function that is capable of keeping the ratio of a main current to a detection current constant even under different operating conditions, and capable of suppressing the voltage dependence of the limited-current value to perform stable overcurrent protection. P-wells are formed so that they are incorporated between main cell IGBTs as sensing cells for current detection on part of the semiconductor substrate on which a large number of main cells are formed integratedly, and current-detecting emitter electrodes connected to the P-wells are connected to an overcurrent-protection circuit and separated from the main emitter electrodes connected to the main IGBT cells. Given such a configuration, the overcurrent flowing into the main cells during a load short circuit in an inverter device is detected as a hole current from the P-wells with a high accuracy of keeping the current ratio to the current in the main cells constant, and moreover, stable overcurrent protection is performed keeping the limited current values suppressed below the short-circuit withstand capability without dependence on the power supply voltage.
摘要翻译：具有过电流限制功能的绝缘栅型双极晶体管，即使在不同的工作条件下也能够使主电流与检测电流的比例保持恒定，并且能够抑制有限电流值的电压依赖性而稳定过电流保护。形成P阱，使得它们被结合在主电池IGBT之间作为在其上集成有大量主电池的部分半导体衬底上进行电流检测的感测单元，以及连接到P阱的电流检测发射极连接到过电流保护电路，并与连接到主IGBT单元的主发射极分离。给出这样的结构，在逆变器装置中的负载短路期间流入主电池的过电流以与主电池中的电流恒定的高精度从P阱检测为空穴电流，而且，在不依赖于电源电压的情况下，将受限电流值保持在短路耐受能力以下，进行稳定的过电流保护。

7. 发明授权

US07462911B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07462911B2
公开(公告)日：2008-12-09
申请号：US11561652
申请日：2006-11-20
申请人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
发明人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2）}×100 <= 75。

8. 发明授权

US06737705B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06737705B2
公开(公告)日：2004-05-18
申请号：US09843251
申请日：2001-04-26
申请人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
发明人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
IPC分类号： H01L29745
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/407
摘要： A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.
摘要翻译：沟槽型IGBT包括硅衬底，硅衬底上的轻掺杂n型漂移层和n型漂移层上的p型基极层。 p型基极层比n型漂移层掺杂更多，由第一区域和第二区域形成。在p型基底层的第一区域的表面部分中选择性地形成N +型源极区域。沟槽从n +型源区的表面通过p型基底层向下到达n型漂移层。栅极氧化膜覆盖每个沟槽的内表面。栅极设置在沟槽中，其中栅电极经由相应的栅氧化膜面对p型基极层。发射极电极与p型基极层和n +型源极区域的第一区域直接接触。集电极设置在硅衬底的背面上。第一区域的宽度与p型基底层的第二区域的宽度的比例为1:2至1:7。该器件通过降低开关损耗同时将其导通电压抑制得低至IEGT的导通电压，从而有助于降低总损耗。

9. 发明授权

US5530277A Insulated-gate bipolar transistor 失效
标题翻译：绝缘栅双极晶体管
公开(公告)号：US5530277A
公开(公告)日：1996-06-25
申请号：US321999
申请日：1994-10-12
申请人： Masahito Otsuki , Shigeyuki Obinata , Yukio Yano
发明人： Masahito Otsuki , Shigeyuki Obinata , Yukio Yano
IPC分类号： H01L29/78 , H01L27/02 , H01L27/04 , H01L29/739 , H01L29/76
CPC分类号： H01L29/7395 , H01L27/0248 , H01L27/0251
摘要： An insulated-gate bipolar transistor is formed of a number of cells integrally formed on a semiconductor substrate. The cells includes main cells with emitter electrodes, and current detection sensing cells situated adjacent to the main cells. Emitter electrodes are formed in an area of the sensing cells to be separated from the emitter electrodes of the main cells, and an overcurrent protection circuit is connected to the emitter electrodes of the sensing cells. When shorting accident occurs, an overcurrent protecting operation is performed such that an overcurrent is accurately detected through the sensing cells and a main current flowing through the main cells is made smaller than a short-circuit withstanding capacity of the IGBT by gate control of the protection circuit.
摘要翻译：绝缘栅双极晶体管由在半导体基板上一体形成的多个单元形成。电池包括具有发射极电极的主电池和位于主电池附近的电流检测感测单元。发射极电极形成在感测单元的与主单元的发射电极分离的区域中，并且过电流保护电路连接到感测单元的发射极。当发生短路事故时，进行过电流保护动作，使得通过感测单元精确地检测出过电流，并且流过主单元的主电流通过栅极控制保护而小于IGBT的短路耐受容量电路。

10. 发明授权

US5459339A Double gate semiconductor device and control device thereof 失效
标题翻译：半导体功率器件
公开(公告)号：US5459339A
公开(公告)日：1995-10-17
申请号：US53650
申请日：1993-04-29
申请人： Ken'ya Sakurai , Masahito Otsuki , Noriho Terasawa , Tadashi Miyasaka , Akira Nishiura , Masaharu Nishiura
发明人： Ken'ya Sakurai , Masahito Otsuki , Noriho Terasawa , Tadashi Miyasaka , Akira Nishiura , Masaharu Nishiura
IPC分类号： H01L29/739 , H01L29/745 , H01L29/749 , H03K17/0812 , H03K17/082 , H03K17/567 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7395 , H01L29/7455 , H01L29/749 , H03K17/08128 , H03K17/0828 , H03K17/567
摘要： A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions. The first conductive type emitter region is formed within the second conductive type emitter region. A second gate electrode of the second MOSFET is formed on the surface of the first conductive type emitter region, the second conductive type emitter region and the first conductive type base region through a gate insulating film. The first gate electrode of the first and third MOSFET is formed on the surface of the first conductive type emitter region, the second conductive type emitter region, the first conductive type base region and the second conductive type base region through a gate insulating film.
摘要翻译：半导体器件晶闸管结构包括第一导电型集电极区域，第二导电型和第一导电型基极区域以及第二导电型发射极区域。第一导电类型区域和第二导电类型区域具有相应的第一和第二多数载流子。第一MOSFET将第二类型多数载流子注入第二导电型基极区域。独立于第一MOSFET的第二个MOSFET被打开和关闭，并从第一导电类型的基极区域提取出第一类型多数载流子。第三MOSFET具有第一栅极电极，其也是第一MOSFET的栅电极，用于从第一导电类型基极区域提取第一多数载流子。第一导电类型和第二导电型发射极区域形成在第一导电类型基极区域内，并且发射极电压可以同时施加到这些发射极区域。第一导电型发射极区域形成在第二导电型发射极区域内。通过栅极绝缘膜，在第一导电型发射极区域，第二导电型发射极区域和第一导电型基极区域的表面上形成第二MOSFET的第二栅电极。第一和第三MOSFET的第一栅极通过栅极绝缘膜形成在第一导电型发射极区域，第二导电型发射极区域，第一导电型基极区域和第二导电型基极区域的表面上。

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