专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06493282B2 Semiconductor integrated circuit 有权
公开(公告)号：US06493282B2
公开(公告)日：2002-12-10
申请号：US09946480
申请日：2001-09-06
申请人： Masahisa Iida , Kiyoto Oota , Yuji Yamasaki , Hakuhei Kawakami
发明人： Masahisa Iida , Kiyoto Oota , Yuji Yamasaki , Hakuhei Kawakami
IPC分类号： G11C700
CPC分类号： G11C7/10 , G11C2207/104
摘要： A semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a DRAM array. In the array, memory cells are arranged in matrix over the first n-well. Each memory cell includes a p-channel MOS access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, word line driver and first n-well.

2. 发明申请

US20060179378A1 Semiconductor integrated circuit and method of testing the same 审中-公开
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US20060179378A1
公开(公告)日：2006-08-10
申请号：US11338684
申请日：2006-01-25
申请人： Masahisa Iida , Yuji Yamasaki
发明人： Masahisa Iida , Yuji Yamasaki
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005
摘要： In this semiconductor integrated circuit, outputs of a fuse for power supply level adjustment and an internal register are selectively switched by a selector, and a selected output is inputted to a reference voltage generating circuit. Hence, the same reference voltage can be generated before and after blowing the fuse. An internal power supply voltage is generated based on this reference voltage. That makes it possible to output the same internal power supply voltage as that after blowing the fuse by using the output of the internal register before blowing the fuse. As the result of this, a redundant relief determination test using the internal power supply can be performed, and by executing a test at the same speed as that of an actual operation using BIST, an error between the internal voltages during a test and during an actual operation can be eliminated, thus achieving a highly accurate redundant relief determination of a marginal bit.
摘要翻译：在该半导体集成电路中，通过选择器选择性地切换用于电源电平调整的熔丝的输出和内部寄存器，并且将选择的输出输入到参考电压产生电路。因此，在熔断器之前和之后可以产生相同的参考电压。基于该参考电压产生内部电源电压。这样可以在熔断保险丝之前，使用内部寄存器的输出，输出与熔断器相同的内部电源电压。其结果，可以进行使用内部电源的冗余放电判定试验，通过以与使用BIST的实际动作相同的速度进行试验，在试验中和内部电压之间产生内部电压之间的误差可以消除实际操作，从而实现边缘位的高度精确的冗余补偿确定。

3. 发明授权

US10160018B2 Method of manufacturing closed-structure part and apparatus for the same 有权
公开(公告)号：US10160018B2
公开(公告)日：2018-12-25
申请号：US14394192
申请日：2012-04-13
申请人： Kazuhiko Higai , Yuji Yamasaki
发明人： Kazuhiko Higai , Yuji Yamasaki
IPC分类号： B21C37/15 , B21D5/01 , B21C37/08 , B21D53/88
摘要： A method manufactures a closed-structure part by forming a flat plate-shaped workpiece into a closed structure including a bottom portion curved along a longitudinal direction. The method includes a first forming step of forming a plurality of first out-of-plane deformed portions and a bent portion, the first out-of-plane deformed portions being formed in a region of the workpiece corresponding to the bottom portion and arranged along the longitudinal direction, each of the out-of-plane deformed portions having a recessed shape or a protruding shape; and a second forming step of squashing the first out-of-plane deformed portions between a pad and a punch such that the region of the workpiece corresponding to the bottom portion is curved and bending bent portions by pressing the punch into a space between dies while the region of the workpiece corresponding to the bottom portion is clamped between the pad and the punch.

4. 发明授权

US09669444B2 Method of manufacturing curvilineal closed structure parts without flange and apparatus for the same 有权
公开(公告)号：US09669444B2
公开(公告)日：2017-06-06
申请号：US14394191
申请日：2012-04-13
申请人： Kazuhiko Higai , Yuji Yamasaki , Toyohisa Shinmiya
发明人： Kazuhiko Higai , Yuji Yamasaki , Toyohisa Shinmiya
IPC分类号： B23K37/00 , B23K37/02 , B23K37/04 , B23K28/00 , B21D22/02 , B21C37/08 , B21C37/15 , B23K31/02 , B21C37/14 , B21C37/16 , B21D5/08 , B21D47/01 , B21D11/08 , B21D11/14
CPC分类号： B21D22/025 , B21C37/0803 , B21C37/14 , B21C37/155 , B21C37/16 , B21D5/086 , B21D11/08 , B21D11/14 , B21D47/01 , B23K31/02
摘要： A method and apparatus manufactures a closed structure part without flange having a curvature and welded edges along a longitudinal direction of the part and further having a varying cross-sectional shape, from two metal plates. Each of two metal plates provided with a curvature along the longitudinal direction of the plate and provided with both ends in a width direction of the plate, are press-formed such that a folding line is formed at positions corresponding to a non-welded bent edge in a cross section of the part, and stacked on each other vertically such that their bulging sides face outward. Their left ends and right ends in the width direction are mutually welded along the longitudinal direction to form welded edges.

5. 发明授权

US09009970B2 Curvilineal closed structure parts and method for manufacturing the same 有权
标题翻译：曲线闭合结构件及其制造方法
公开(公告)号：US09009970B2
公开(公告)日：2015-04-21
申请号：US13391850
申请日：2010-09-15
申请人： Kazuhiko Higai , Takayuki Futatsuka , Yoshikiyo Tamai , Takaaki Hira , Yuji Yamasaki
发明人： Kazuhiko Higai , Takayuki Futatsuka , Yoshikiyo Tamai , Takaaki Hira , Yuji Yamasaki
IPC分类号： B21D21/00 , B21D47/01 , B21C37/08 , B21D11/20 , B21D47/04 , B21D51/06
CPC分类号： B21D47/01 , B21C37/0803 , B21D11/20 , B21D47/04 , B21D51/06 , Y10T29/49391
摘要： A method for manufacturing includes a polygonal shape closed structure part with a bent shape in the longitudinal direction only by press forming. The method uses two metal plates for manufacturing a curvilineal closed structure part and includes a press forming process of forming straight or bent folding lines in the longitudinal direction of the two metal plates at positions corresponding to a polygonal bent shape with a flange formed at least at one of the ends of the width direction of each plate, a process of forming a closed structure by laying the two metal plates to overlap each other flange to flange and end to end for ends without flanges and by welding the portions laid to overlap each other in the longitudinal direction of the metal plates, and a process of forming a polygonal shape closed structure having a bent shape in the longitudinal direction by holding both ends of the closed structure and by compressing it toward its central axis.
摘要翻译：一种制造方法包括仅通过冲压成形在纵向上具有弯曲形状的多边形封闭结构部分。该方法使用两个金属板来制造曲线性封闭结构部件，并且包括压制成型工艺，该方法是在对应于多边形弯曲形状的位置处在两个金属板的纵向上形成直的或弯曲的折叠线，凸缘至少形成在每个板的宽度方向的端部之一，通过将两个金属板铺设成彼此凸缘到凸缘并且端部到端而形成闭合结构的过程而不具有凸缘并且通过焊接彼此重叠的部分在金属板的纵向方向上，并且通过保持封闭结构的两端并且朝向其中心轴线压缩而形成具有在纵向方向上的弯曲形状的多边形封闭结构的工艺。

6. 发明申请

US20120171506A1 CURVED PARTS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：弯曲部件及其制造方法
公开(公告)号：US20120171506A1
公开(公告)日：2012-07-05
申请号：US13395477
申请日：2010-09-28
申请人： Takayuki Futatsuka , Kazuhiko Higai , Yoshikiyo Tamai , Takaaki Hira , Takeshi Fujita , Yuji Yamasaki
发明人： Takayuki Futatsuka , Kazuhiko Higai , Yoshikiyo Tamai , Takaaki Hira , Takeshi Fujita , Yuji Yamasaki
IPC分类号： B21C1/00 , B21D31/00
CPC分类号： B21D5/015 , B21C37/14 , B21D47/01 , E04C3/07 , E04C2003/0413 , E04C2003/0439 , E04C2003/0465 , Y10T428/12229
摘要： A curved-part forming method for obtaining a curved part by performing forming on a blank formed of a single metal plate, the method including a bending process in which the blank having a curved outline corresponding to a curve of the curved part in a longitudinal direction is bent into a sectional shape corresponding to a division portion of a sectional shape of the curved part; and a joining process in which two or more portions obtained by the bending process are joined together.
摘要翻译：一种用于通过在由单个金属板形成的坯料上进行成形来获得弯曲部分的弯曲部分形成方法，所述弯曲部分形成方法包括弯曲过程，其中所述坯料具有与所述弯曲部分的纵向方向上的曲线相对应的弯曲轮廓弯曲成对应于弯曲部分的截面形状的分割部分的截面形状; 以及通过弯曲处理获得的两个以上部分连接在一起的接合工序。

7. 发明申请

US20050205983A1 Semiconductor memory device and multi-chip module comprising the semiconductor memory device 有权
标题翻译：半导体存储器件和包括半导体存储器件的多芯片模块
公开(公告)号：US20050205983A1
公开(公告)日：2005-09-22
申请号：US11131385
申请日：2005-05-18
申请人： Kenichi Origasa , Yuji Yamasaki
发明人： Kenichi Origasa , Yuji Yamasaki
IPC分类号： G11C17/00 , G11C5/06 , G11C11/22 , G11C11/401 , G11C11/407 , G11C11/41 , G11C11/413 , G11C16/04 , G11C16/06 , G11C29/48 , H01L21/822 , H01L21/8242 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/10 , H01L27/108 , H01L23/02
CPC分类号： H01L25/18 , G11C5/06 , G11C29/48 , G11C2207/105 , H01L25/0652 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.
摘要翻译：在由半导体芯片构成并与另一半导体芯片的表面重合以连接在一起的半导体存储器件中，设置在半导体存储器件中的控制电路设置有具有多个焊盘的芯片连接器部分。芯片连接器部分形成为具有对应于设置在半导体存储器件中的存储单元阵列的最大容量的配置，并且即使当存储单元阵列具有小于等于的容量时，也始终确定焊盘的位置和数量最大容量。包含芯片连接器部分的控制电路也总是被确定，以便控制从具有最大容量的存储单元阵列读取和写入数据，而与所提供的存储单元阵列的容量无关。

8. 发明授权

US06797411B2 Galvanized steel sheet, method for manufacturing the same, and method for manufacturing press-formed product 有权
标题翻译：镀锌钢板，其制造方法以及压制成形品的制造方法
公开(公告)号：US06797411B2
公开(公告)日：2004-09-28
申请号：US10465461
申请日：2003-06-18
申请人： Yasuhiro Sodani , Yukio Kimura , Masayasu Ueno , Shogo Tomita , Hisato Noro , Kaoru Sato , Yoshiharu Sugimoto , Satoru Ando , Masaki Tada , Junichi Inagaki , Masaaki Yamashita , Yuji Yamasaki
发明人： Yasuhiro Sodani , Yukio Kimura , Masayasu Ueno , Shogo Tomita , Hisato Noro , Kaoru Sato , Yoshiharu Sugimoto , Satoru Ando , Masaki Tada , Junichi Inagaki , Masaaki Yamashita , Yuji Yamasaki
IPC分类号： B21D2202
CPC分类号： C23C22/78 , B24C1/06 , B24C1/086 , B24C1/10 , B24C3/12 , C23C2/26 , C23C2/265 , Y10T428/12611 , Y10T428/12799 , Y10T428/12993
摘要： The method for manufacturing galvanized steel sheet has a step of adjusting the surface texture thereof by blasting solid particles against the surface thereof. The surface texture is defined by at least one parameter selected from the group of parameters consisting of mean roughness Ra on the surface of steel sheet, peak count PPI on the surface of steel sheet, and filtered centerline waviness Wca on the surface of steel sheet. The galvanized steel sheet has a surface in dimple-pattern texture.
摘要翻译：制造镀锌钢板的方法具有通过在其表面上喷射固体颗粒来调节其表面质地的步骤。表面纹理由选自钢板表面的平均粗糙度Ra，钢板表面的峰值PPI，钢板表面的过滤的中心线波纹Wca的参数组中的至少一个参数定义。镀锌钢板具有凹痕图案纹理。

9. 发明授权

US06570802B2 Semiconductor memory device 有权
公开(公告)号：US06570802B2
公开(公告)日：2003-05-27
申请号：US10008709
申请日：2001-11-13
申请人： Hidefumi Ohtsuka , Yuji Yamasaki , Tomonori Fujimoto
发明人： Hidefumi Ohtsuka , Yuji Yamasaki , Tomonori Fujimoto
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device including a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit. The first internal address generation circuit generates a refresh address of the entire memory region, and the second internal address generation circuit generates a refresh address of a certain part of the regions. By carrying out refresh of only a part of the memory required to be retained, the electric power consumption can be reduced.

10. 发明授权

US06507529B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06507529B2
公开(公告)日：2003-01-14
申请号：US10003430
申请日：2001-12-06
申请人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
发明人： Tomonori Fujimoto , Kiyoto Ohta , Yuji Yamasaki
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.
摘要翻译：一种能够刷新多个存储单元的半导体器件。在操作中，当请求数据读取操作时，a /行选择控制信号被输入到行选择控制电路的设置/复位电路，由此输出H电平隐藏刷新控制信号，并且内部行选择控制信号转换到 H级。结果，选择预期的字线，并且启动刷新操作。然后，在感测操作完成之后，通过延迟电路将感测放大器激活完成信号SEND输入到设置/复位电路，并且内部行选择控制信号转换到L电平。在通过三个延迟电路之后，读出放大器激活完成信号SEND被输入到另一个设置/复位电路，并且RW行选择控制信号转换到H电平，从而进行数据读取操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式