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1. 发明授权

US06867090B2 Semiconductor device and method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06867090B2
公开(公告)日：2005-03-15
申请号：US10421903
申请日：2003-04-24
申请人： Masahiko Hiratani , Shinichiro Kimura , Tomoyuki Hamada
发明人： Masahiko Hiratani , Shinichiro Kimura , Tomoyuki Hamada
IPC分类号： C23C16/40 , H01L21/02 , H01L21/316 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/02194 , H01L21/02183 , H01L21/02192 , H01L21/02271 , H01L21/31604 , H01L21/31691 , H01L27/10814 , H01L28/40
摘要： By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.
摘要翻译：通过使用五氧化二钽和五氧化铌的固溶体作为安装在半导体器件中的电容器中的上电极和下电极之间的电介质膜，可以简化电容器结构以提高半导体器件的可靠性，同时减少生产成本。

2. 发明授权

US06576928B2 Semiconductor device capacitor with high permittivity tantalum pentoxide/niobium pentoxide dielectric 失效
标题翻译：具有高介电常数五氧化二钽/五氧化铌电介质的半导体器件电容器
公开(公告)号：US06576928B2
公开(公告)日：2003-06-10
申请号：US09930144
申请日：2001-08-16
申请人： Masahiko Hiratani , Shinichiro Kimura , Tomoyuki Hamada
发明人： Masahiko Hiratani , Shinichiro Kimura , Tomoyuki Hamada
IPC分类号： H01L27108
CPC分类号： H01L21/02194 , H01L21/02183 , H01L21/02192 , H01L21/02271 , H01L21/31604 , H01L21/31691 , H01L27/10814 , H01L28/40
摘要： By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.
摘要翻译：通过使用五氧化二钽和五氧化铌的固溶体作为安装在半导体器件中的电容器中的上电极和下电极之间的电介质膜，可以简化电容器结构以提高半导体器件的可靠性，同时减少生产成本。

3. 发明申请

US20100232231A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20100232231A1
公开(公告)日：2010-09-16
申请号：US12787158
申请日：2010-05-25
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

4. 发明申请

US20100135080A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20100135080A1
公开(公告)日：2010-06-03
申请号：US12648796
申请日：2009-12-29
申请人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

5. 发明申请

US20100097246A1 INPUT DEVICE AND KEYBOARD DEVICE HAVING ILLUMINATION FUNCTION 失效
标题翻译：具有照明功能的输入设备和键盘设备
公开(公告)号：US20100097246A1
公开(公告)日：2010-04-22
申请号：US12579903
申请日：2009-10-15
申请人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
发明人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
IPC分类号： H03M11/00
CPC分类号： G06F3/0202 , H01H13/83 , H01H2219/044 , H01H2219/056 , H01H2219/06 , H01H2219/062
摘要： An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.
摘要翻译：输入装置包括多个操作部分; 由操作部分操纵以输入功能的输入功能部分; 面向所述多个操作部的后侧的导光片; 以及向所述导光片施加光的光源，其中与所述导光片的面对所述操作部的前表面相对的后表面设置有多个凹陷部，所述凹部被压向所述导光片的内部，其特征在于，每个凹部具有圆形开口和内表面，该内表面是光滑的凹曲面，并且其中通过导光片的内部传播的光被内表面朝向导光片的内部反射，并且光从导光片的前表面施加到操作部。

6. 发明申请

US20100084709A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100084709A1
公开(公告)日：2010-04-08
申请号：US11993862
申请日：2006-06-30
申请人： Ryuta Tsuchiya , Shinichiro Kimura
发明人： Ryuta Tsuchiya , Shinichiro Kimura
IPC分类号： H01L29/786 , H01L21/336 , H01L21/86
CPC分类号： H01L27/12 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207
摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
摘要翻译：当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

7. 发明申请

US20080258218A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080258218A1
公开(公告)日：2008-10-23
申请号：US12105226
申请日：2008-04-17
申请人： Yusuke Morita , Yoshinobu Kimura , Ryuta Tsuchiya , Nobuyuki Sugii , Shinichiro Kimura
发明人： Yusuke Morita , Yoshinobu Kimura , Ryuta Tsuchiya , Nobuyuki Sugii , Shinichiro Kimura
IPC分类号： H01L27/01
CPC分类号： H01L29/045 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.
摘要翻译：提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

8. 发明授权

US07212444B2 Semiconductor nonvolatile memory device 有权
公开(公告)号：US07212444B2
公开(公告)日：2007-05-01
申请号：US11137518
申请日：2005-05-26
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

9. 发明申请

US20070040208A1 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20070040208A1
公开(公告)日：2007-02-22
申请号：US11589095
申请日：2006-10-30
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L29/76
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

10. 发明授权

US07132718B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US07132718B2
公开(公告)日：2006-11-07
申请号：US10726507
申请日：2003-12-04
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

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