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1. 发明授权

US4240096A Fluorine-doped P type silicon 失效
标题翻译：氟掺杂P型硅
公开(公告)号：US4240096A
公开(公告)日：1980-12-16
申请号：US952777
申请日：1978-10-19
申请人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
发明人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
IPC分类号： H01L21/265 , H01L21/761 , H01L29/167 , H01L29/8605
CPC分类号： H01L21/26506 , H01L21/761 , H01L29/167 , H01L29/8605
摘要： A semiconductor device comprising a fluorine ion implantation region which is selectively formed in a semiconductor region and further activated. The fluorine ion implantation region is adapted for use as a high resistance layer or electrical isolation layer.
摘要翻译：一种半导体器件，包括选择性地形成在半导体区域中并进一步活化的氟离子注入区。氟离子注入区适合用作高电阻层或电隔离层。

2. 发明授权

US4200969A Semiconductor device with multi-layered metalizations 失效
标题翻译：具有多层金属化的半导体器件
公开(公告)号：US4200969A
公开(公告)日：1980-05-06
申请号：US831873
申请日：1977-09-09
申请人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
发明人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/3213 , H01L21/768 , B01J17/00
CPC分类号： H01L21/76838 , H01L21/32134 , H01L21/32136 , Y10S438/945 , Y10T29/49156
摘要： There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.
摘要翻译：提供了一种在半导体主体的主表面上具有交替层叠的绝缘和导电层的半导体器件和用于制造半导体器件的工艺。在制造过程中，最终形成的导电层以外的导电层各自形成为包括蚀刻速率不同的至少两个金属层的层压体。照相雕刻过程遵循此步骤。在薄层中，更靠近半导体本体的金属层的蚀刻速率比形成在其上的金属层的蚀刻速率低。在半导体器件中，除了远离半导体主体的导电层之外的导电层的侧壁发散，朝向半导体本体变宽。

3. 发明授权

US4507673A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4507673A
公开(公告)日：1985-03-26
申请号：US534361
申请日：1983-09-21
申请人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
发明人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/513 , H01L29/51 , H01L29/792
摘要： A semiconductor memory device is disclosed which comprises:a semiconductor substrate of n conductivity type;source and drain regions of p.sup.+ conductivity type formed in the substrate;a first gate insulation film of silicon dioxide (SiO.sub.2) formed on the substrate; anda second gate insulation film of silicon carbide (SiC) formed on the first gate insulation film.
摘要翻译：公开了一种半导体存储器件，其包括：n导电类型的半导体衬底; 在衬底中形成p +导电类型的源区和漏区; 在基板上形成的二氧化硅（SiO 2）的第一栅极绝缘膜; 以及形成在第一栅极绝缘膜上的碳化硅（SiC）的第二栅极绝缘膜。

4. 发明授权

US4560642A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4560642A
公开(公告)日：1985-12-24
申请号：US632239
申请日：1984-07-19
申请人： Toshio Yonezawa , Takashi Ajima , Shunichi Hiraki , Yutaka Koshino , Yoshitami Oka
发明人： Toshio Yonezawa , Takashi Ajima , Shunichi Hiraki , Yutaka Koshino , Yoshitami Oka
IPC分类号： H01L21/033 , H01L21/311 , H01L21/314 , B05D1/32
CPC分类号： H01L21/31144 , H01L21/033 , H01L21/31111 , H01L21/31116 , H01L21/314 , Y10S438/945 , Y10S438/95 , Y10S438/951
摘要： A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：选择性地施加具有规定穿孔图案的碳化硅膜作为掩模膜，以蚀刻二氧化硅膜或将杂质扩散到衬底中。

5. 发明授权

US4521256A Method of making integrated devices having long and short minority carrier lifetimes 失效
标题翻译：制造具有少量载体寿命长短的集成器件的方法
公开(公告)号：US4521256A
公开(公告)日：1985-06-04
申请号：US531620
申请日：1983-09-13
申请人： Shunichi Hiraki , Hiroshi Kinoshita , Kuniaki Kumamaru , Shigeo Koguchi , Toshio Yonezawa
发明人： Shunichi Hiraki , Hiroshi Kinoshita , Kuniaki Kumamaru , Shigeo Koguchi , Toshio Yonezawa
IPC分类号： H01L21/322 , H01L21/263 , H01L21/265 , H01L21/268 , H01L21/324
CPC分类号： H01L21/324 , H01L21/263 , H01L21/2636 , H01L21/26506 , H01L21/26513 , H01L21/26546 , H01L21/268 , Y10S148/024 , Y10S148/046 , Y10S148/081
摘要： A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a semiconductor substrate to shorten the minority carrier lifetime. Then ions are selectively implanted into a region in which the minority carrier lifetime is to be recovered. Finally, the resultant structure is annealed.
摘要翻译：一种用于制造半导体器件的方法，其中可以在半导体器件中选择性地改变少数载流子寿命。辐射束照射到半导体衬底的表面上以缩短少数载流子寿命。然后将离子选择性地注入到将要回收少数载流子寿命的区域中。最后，将所得结构退火。

6. 发明授权

US4485393A Semiconductor device with selective nitride layer over channel stop 失效
标题翻译：具有通道停止的选择性氮化物层的半导体器件
公开(公告)号：US4485393A
公开(公告)日：1984-11-27
申请号：US267420
申请日：1981-05-26
申请人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
发明人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L29/73 , H01L21/31 , H01L21/331 , H01L29/06 , H01L29/34
CPC分类号： H01L29/0638
摘要： A semiconductor device comprises a semiconductor body of one conductivity type, at least one semiconductor region of the opposite conductivity type formed in the semiconductor body and having a surface flush with the surface of the semiconductor body, an insulative or semi-insulative film formed on the semiconductor body or semiconductor region through a passivation layer and having a fixed charge, positive or negative, and an electrode metal layer connected to at least one of the semiconductor body and region and formed locally on the film directly or through a passivation layer. The semiconductor body or region is of N conductivity type when the film has a positive fixed charge and of P conductivity type when the film has a negative fixed charge.
摘要翻译：半导体器件包括一个导电类型的半导体本体，形成在半导体本体中的具有相反导电类型的至少一个半导体区域，并具有与半导体本体的表面齐平的表面，形成在半导体本体的表面上的绝缘或半绝缘膜半导体本体或半导体区域通过钝化层并具有固定电荷，正极或负极以及连接到半导体主体和区域中的至少一个的电极金属层，并且直接或通过钝化层局部形成在膜上。当膜具有负固定电荷时，当膜具有正固定电荷和P导电类型时，半导体本体或区域为N导电类型。

7. 发明授权

US4351894A Method of manufacturing a semiconductor device using silicon carbide mask 失效
标题翻译：使用碳化硅掩模制造半导体器件的方法
公开(公告)号：US4351894A
公开(公告)日：1982-09-28
申请号：US262938
申请日：1981-05-12
申请人： Toshio Yonezawa , Takashi Ajima , Shunichi Hiraki , Yutaka Koshino , Yoshitami Oka
发明人： Toshio Yonezawa , Takashi Ajima , Shunichi Hiraki , Yutaka Koshino , Yoshitami Oka
IPC分类号： H01L21/033 , H01L21/311 , H01L21/314 , H01L21/316
CPC分类号： H01L21/31144 , H01L21/033 , H01L21/31111 , H01L21/31116 , H01L21/314 , Y10S438/945 , Y10S438/95 , Y10S438/951
摘要： A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：选择性地施加具有规定穿孔图案的碳化硅膜作为掩模膜，以蚀刻二氧化硅膜或将杂质扩散到衬底中。

8. 发明授权

US4589004A Semiconductor device monolithically comprising a V-MOSFET and bipolar transistor isolated from each other 失效
标题翻译：半导体器件单片地包括彼此隔离的V-MOSFET和双极晶体管
公开(公告)号：US4589004A
公开(公告)日：1986-05-13
申请号：US665506
申请日：1984-10-30
申请人： Seiji Yasuda , Toshio Yonezawa , Shunichi Hiraki , Masafumi Miyagawa
发明人： Seiji Yasuda , Toshio Yonezawa , Shunichi Hiraki , Masafumi Miyagawa
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/78 , H01L27/02
CPC分类号： H01L21/761 , H01L21/74 , H01L27/0623 , H01L29/7802 , H01L29/7809 , H01L29/0847
摘要： A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.
摘要翻译：包括高耐压垂直MOSFET和低电压耐受元件的半导体器件都形成在单个芯片上。在形成垂直MOSFET的区域中形成高杂质浓度的掩埋层，并且在形成低压耐受元件的区域中形成另一个杂质浓度较高的掩埋层。这些埋层具有不同的厚度，从而降低了与垂直MOSFET相邻的电路的串联电阻，而不降低垂直MOSFET的耐受电压。

9. 发明授权

US4542400A Semiconductor device with multi-layered structure 失效
标题翻译：具有多层结构的半导体器件
公开(公告)号：US4542400A
公开(公告)日：1985-09-17
申请号：US528473
申请日：1983-09-01
申请人： Shunichi Hiraki , Kuniaki Kumamaru , Yutaka Koshino , Toshio Yonezawa
发明人： Shunichi Hiraki , Kuniaki Kumamaru , Yutaka Koshino , Toshio Yonezawa
IPC分类号： H01L29/73 , H01L21/283 , H01L21/31 , H01L21/314 , H01L21/331 , H01L23/29 , H01L23/58 , H01L29/34 , H01L23/30 , H01L29/40
CPC分类号： H01L23/58 , H01L21/31 , H01L23/291 , H01L2924/0002
摘要： A semiconductor device comprising a substrate means, a semiconductor layer of an N conductivity type formed on the substrate means, a first semiconductor region of a P conductivity type formed in the semiconductor layer and having its exposed major surface, a second semiconductor region of the N conductivity type formed in the first semiconductor region and having its exposed major surface, a first insulation layer means having a positive polarity type of charge and formed on the N semiconductor layer, and a second insulation layer means having a negative polarity type of charge and formed on the P semiconductor region.
摘要翻译：一种半导体器件，包括基板装置，形成在所述基板装置上的N导电类型的半导体层，形成在所述半导体层中并具有其暴露的主表面的P导电类型的第一半导体区域，所述N的第二半导体区域导电类型形成在第一半导体区域中并且具有暴露的主表面，具有正极性类型的电荷并形成在N半导体层上的第一绝缘层装置和形成为负极性类型的电荷的第二绝缘层装置在P半导体区域。

10. 发明授权

US4379726A Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition 失效
标题翻译：利用外扩散和外延沉积制造半导体器件的方法
公开(公告)号：US4379726A
公开(公告)日：1983-04-12
申请号：US147334
申请日：1980-05-06
申请人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
发明人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L21/8222 , H01L21/22 , H01L21/331 , H01L21/74 , H01L21/761 , H01L27/082 , H01L29/73 , H01L21/76
CPC分类号： H01L21/74 , H01L21/2205 , H01L21/761
摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming a first high impurity concentration region of a conductivity type opposite to the conductivity type of a semiconductor substrate in the substrate along the principal surface thereof, depositing a first epitaxial layer of the same conductivity type as the substrate on the entire principal surface thereof, forming a low impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a surface portion thereof corresponding to the first high impurity concentration region, forming a second high impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a different surface portion thereof, forming a second epitaxial layer of the opposite conductivity type to the substrate on the first epitaxial layer, thermally treating the resultant intermediate device to cause diffusion of the impurities in the first and second high impurity concentration region into the respective first and second epitaxial layers and also causing diffusion of the impurity in the low impurity concentration region into the entire portion of the first epitaxial layer corresponding to the first high impurity concentration region, and forming an element isolation region of the same conductivity type as the substrate in the second epitaxial layer such that the element isolation region reaches the first epitaxial layer.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：沿着其主表面在衬底中形成与半导体衬底的导电类型相反的导电类型的第一高杂质浓度区域，沉积其第一外延层导电类型作为其整个主表面上的基板，沿着与第一高杂质浓度区域相对应的表面部分，在第一外延层中形成相反导电类型的低杂质浓度区域，形成第二高杂质在与所述第一外延层不同的表面部分与所述第一外延层中的所述衬底相反的导电类型的浓度区域上形成与所述第一外延层上的所述衬底相反的导电类型的第二外延层，热处理所得到的中间器件以引起扩散的杂质在fi 第一和第二高杂质浓度区域进入相应的第一和第二外延层，并且还引起低杂质浓度区域中的杂质扩散到对应于第一高杂质浓度区域的第一外延层的整个部分中，并且形成元素隔离区域与第二外延层中的衬底具有相同的导电类型，使得元件隔离区域到达第一外延层。

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