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1. 发明授权

US6114866A Semiconductor device test board and method for evaluating semiconductor devices 失效
标题翻译：半导体器件测试板和半导体器件评估方法
公开(公告)号：US6114866A
公开(公告)日：2000-09-05
申请号：US18445
申请日：1998-02-04
申请人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
发明人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , G01R35/00 , G01R31/02
CPC分类号： G01R31/2863 , H01L2924/0002
摘要： A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test. Each indicator arm changes its position if a failure has occurred in the semiconductor device during the test, and retains one of the two positions until after the test board is taken out of the burn-in oven. Thus, the test result can be determined after taking out the test board from the burn-in oven.
摘要翻译：半导体器件测试板解决了常规测试板的问题，因为只有在将测试板从老化炉中取出之前，才能识别通过烧录程序获得的测试结果。因此，常规测试板需要额外的步骤，以便在从老化炉中取出测试板后检查测试结果。这个额外的步骤可以防止测试的效率得到改善。本测试板的一个实施例具有指示臂，每个指示臂可旋转地安装在测试板上的枢轴上，用于响应于信号线上的信号，指示与其相关联的半导体器件的测试结果。当在测试期间与其相关联的半导体器件中没有发生故障时，每个指示器臂保持其静止位置。如果在测试期间在半导体器件中发生故障，则每个指示臂改变其位置，并且保持两个位置中的一个，直到将测试板从老化炉中取出。因此，可以在从老化炉中取出测试板之后确定测试结果。

2. 发明授权

US6043522A Field effect transistor array including doped two-cell isolation region for preventing latchup 失效
标题翻译：场效应晶体管阵列包括用于防止闭锁的掺杂的二单元隔离区
公开(公告)号：US6043522A
公开(公告)日：2000-03-28
申请号：US61090
申请日：1998-04-16
申请人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
发明人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105
CPC分类号： H01L27/105 , H01L21/761 , Y10S257/901 , Y10S257/909
摘要： A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.
摘要翻译：能够解决现有的半导体器件的问题的半导体器件的原因在于，由于包括一对相邻地设置的一对N阱和P阱的每个单元需要单独地闭锁的对策，所以不能期望高密度积分。高密度集成防止锁定的有效对策。本半导体装置将N个阱和P个阱的排列方向相邻的两个电池相反地配置，使得两个相邻电池的两个P阱（或两个N阱）相继配置，并且包括隔离层延伸穿过两个相邻的电池以封闭两个连续设置的P阱，从而将两个P阱与衬底共同隔离。

3. 发明授权

US5973953A Semiconductor memory device having improved bit line structure 失效
标题翻译：具有改进的位线结构的半导体存储器件
公开(公告)号：US5973953A
公开(公告)日：1999-10-26
申请号：US38278
申请日：1998-03-11
申请人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
发明人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
IPC分类号： H01L21/3205 , G11C5/06 , H01L21/8242 , H01L23/52 , H01L27/108
CPC分类号： G11C5/063
摘要： A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.
摘要翻译：半导体存储器件被构造成使得当第一布线层提供第一公共互补数据线对的位线并且第三布线层提供第二公共互补数据线对的位线时，第二布线层使得第二公共互补数据线对的位线和位线之间的重叠区域等于第一公共互补数据线对的位线，以及第一公共补充数据线对的位线和位线之间的重叠区域互补数据线对等于第二公共互补数据线对的位线。

4. 发明授权

US6040614A Semiconductor integrated circuit including a capacitor and a fuse element 失效
标题翻译：包括电容器和熔丝元件的半导体集成电路
公开(公告)号：US6040614A
公开(公告)日：2000-03-21
申请号：US33611
申请日：1998-03-03
申请人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
发明人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/105 , H01L27/108 , H01L29/40
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/108 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.
摘要翻译：半导体集成电路包括位于绝缘层上的熔丝元件。绝缘层的表面基本上是光滑的。绝缘层位于电容器的上方。接线位于绝缘层上。熔丝元件和布线包括相同的材料。

5. 发明授权

US06545934B2 Semiconductor memory device having configuration suited for high integration 有权
公开(公告)号：US06545934B2
公开(公告)日：2003-04-08
申请号：US09840175
申请日：2001-04-24
申请人： Takekazu Yamashita , Michio Nakajima
发明人： Takekazu Yamashita , Michio Nakajima
IPC分类号： G11C800
CPC分类号： G11C5/025
摘要： A semiconductor memory device includes a plurality of regions. Each region includes memory cell arrays, an input/output circuit zone, column decoders, and a row decoder. The input/output circuit zone is placed between the memory cell arrays. The input/output circuit zone inputs or outputs data to or from the memory cell arrays selectively. As a result, high integration is realized with ease.

6. 发明授权

US06724237B2 Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity 有权
标题翻译：用于多芯片封装的半导体集成电路，具有优化内部驱动能力的手段
公开(公告)号：US06724237B2
公开(公告)日：2004-04-20
申请号：US10212842
申请日：2002-08-07
申请人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
发明人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
IPC分类号： G01R3127
CPC分类号： H03K19/017581 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H03K17/164 , Y10T307/50 , H01L2924/00014
摘要： A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.
摘要翻译：半导体集成电路可以可变地设置在多芯片封装内使用的内部输入/输出端子和内部输出端子的全部或部分的驱动功率。在包装之前，可以在单个晶片测试时增加驱动功率，以充分驱动连接在测试器与内部输入/输出端子和内部输出端子之间的负载，并且可以降低封装后的驱动功率。可以防止噪音和功耗的增加。

7. 发明授权

US06756803B2 Semiconductor device downsizing its built-in driver 失效
标题翻译：半导体器件缩小其内置驱动器
公开(公告)号：US06756803B2
公开(公告)日：2004-06-29
申请号：US10330072
申请日：2002-12-30
申请人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
发明人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
IPC分类号： G01R3102
CPC分类号： G01R31/2884 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.
摘要翻译：半导体器件包括第一焊盘，第二焊盘，第一缓冲器和第二缓冲器。第一焊盘以多芯片封装连接到另一半导体器件，并且第二焊盘在晶片测试中进行探测连接。第一缓冲器驱动连接到第一焊盘的另一个半导体器件。由第一缓冲器驱动的第二缓冲器以大于第一缓冲器的驱动功率的驱动功率驱动连接到第二焊盘的测试仪的负载电容，并且由控制信号控制其主动/不活动状态。半导体器件可以提供晶片测试所需的驱动功率，并驱动另一半导体器件，防止产生驱动噪声并抑制多芯片封装的正常工作中的电流消耗。

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