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1. 发明授权

US06329703B1 Contact between a monocrystalline silicon region and a polycrystalline silicon structure and method for producing such a contact 失效
标题翻译：单晶硅区域和多晶硅结构之间的接触以及用于制造这种接触的方法
公开(公告)号：US06329703B1
公开(公告)日：2001-12-11
申请号：US09030227
申请日：1998-02-25
申请人： Martin Schrems , Kai Wurster , Klaus-Dieter Morhard , Joachim Hoepfner
发明人： Martin Schrems , Kai Wurster , Klaus-Dieter Morhard , Joachim Hoepfner
IPC分类号： H01L2980
CPC分类号： H01L27/10867 , H01L21/76895
摘要： A contact between a polycrystalline silicon structure and a monocrystalline silicon region is produced by doping the silicon structure in amorphous or polycrystalline form and/or doping the monocrystalline silicon region with a dopant, in particular with oxygen, in such a concentration that a solubility limit is exceeded. In a subsequent heat treatment, dopant precipitations are formed which either control grain growth in the polycrystalline silicon layer or prevent a propagation of crystal faults into a substrate in the monocrystalline silicon region. Such a contact can be used, in particular, as a buried strap in a DRAM trench cell.
摘要翻译：多晶硅结构和单晶硅区域之间的接触是通过以非晶态或多晶形式掺杂硅结构和/或用掺杂剂（特别是氧）掺杂单晶硅区域来产生的，其浓度使得溶解度极限为超过了在随后的热处理中，形成掺杂剂沉淀，其控制多晶硅层中的晶粒生长或者防止晶体缺陷传播到单晶硅区域中的衬底中。特别地，这种接触可以用作DRAM沟槽单元中的埋入带。

2. 发明授权

US6068928A Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method 失效
标题翻译：通过该方法制造多晶硅结构体和多晶硅层的方法
公开(公告)号：US6068928A
公开(公告)日：2000-05-30
申请号：US30406
申请日：1998-02-25
申请人： Martin Schrems , Kai Wurster , Klaus-Dieter Morhard , Joachim Hoepfner
发明人： Martin Schrems , Kai Wurster , Klaus-Dieter Morhard , Joachim Hoepfner
IPC分类号： H01L21/768 , H01L21/20 , H01L21/265 , H01L21/28 , H01L21/285 , B32B9/04 , H01L21/36 , H01L21/425
CPC分类号： H01L21/28525 , Y10T428/12528
摘要： A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.
摘要翻译：一种多晶硅结构体和多晶硅层的制造方法，其特征在于，通过首先以非晶态或多晶形式形成所述一次硅结构的方法制造多晶硅结构体，以及特别是用氧掺杂所述结构，其浓度超过溶解度极限。在随后的热处理中，形成控制正在生产的二级结构中的晶粒生长的掺杂剂沉淀。特别地，这种接触多晶硅结构可以用作单晶硅区域的连接。

3. 发明授权

US06828191B1 Trench capacitor with an insulation collar and method for producing a trench capacitor 失效
标题翻译：具有绝缘环的沟槽电容器和用于制造沟槽电容器的方法
公开(公告)号：US06828191B1
公开(公告)日：2004-12-07
申请号：US09363277
申请日：1999-07-28
申请人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
发明人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.
摘要翻译：特别是在半导体存储单元中使用的沟槽电容器具有形成在衬底中的沟槽; 形成在所述沟槽的上部区域中的绝缘套环; 在作为第一电容器板的基板区域中的可选掩埋板; 衬在沟槽的下部区域的绝缘层和作为电容器电介质的绝缘套管; 作为第二电容器板填充到所述沟槽中的导电的第二填充材料; 以及在衬底的表面下方的埋入接触。衬底在其掩埋接触区域的表面下方具有通过注入，等离子体掺杂和/或气相沉积引入的掺杂区域。隧道层，特别是氧化物，氮化物或氮氧化物层优选形成在埋入触点的界面处。还提供了一种制造沟槽电容器的方法。

4. 发明授权

US06509599B1 Trench capacitor with insulation collar and method for producing the trench capacitor 有权
标题翻译：具有绝缘环的沟槽电容器和用于生产沟槽电容器的方法
公开(公告)号：US06509599B1
公开(公告)日：2003-01-21
申请号：US09232081
申请日：1999-01-15
申请人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
发明人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact.
摘要翻译：特别是在半导体存储单元中使用的沟槽电容器具有形成在衬底中的沟槽; 形成在所述沟槽的上部区域中的绝缘套环; 在作为第一电容器板的基板区域中的可选掩埋板; 衬在沟槽的下部区域的绝缘层和作为电容器电介质的绝缘套管; 作为第二电容器板填充到所述沟槽中的导电的第二填充材料; 以及在衬底的表面下方的埋入接触。衬底在其掩埋接触区域的表面下方具有通过注入，等离子体掺杂和/或气相沉积引入的掺杂区域。隧道层，特别是氧化物，氮化物或氮氧化物层优选形成在埋入触点的界面处。

5. 发明授权

US06548850B1 Trench capacitor configuration and method of producing it 失效
标题翻译：沟槽电容器配置及其制造方法
公开(公告)号：US06548850B1
公开(公告)日：2003-04-15
申请号：US09677324
申请日：2000-09-29
申请人： Stefan Gernhard , Martin Schrems , Klaus-Dieter Morhard
发明人： Stefan Gernhard , Martin Schrems , Klaus-Dieter Morhard
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A trench capacitor is formed in a substrate and includes a trench having an upper region and a lower region. An insulating collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A buried plate is formed around the lower region of the trench as an outer capacitor electrode. A dielectric layer, which forms the capacitor dielectric, lines the lower region of the trench and the insulating collar. A conductive trench filling is put into the trench. A conductive contact layer of tungsten nitride is provided above the insulating collar, between the substrate and the conductive trench filling, and acts as a diffusion barrier. This makes it possible to provide the trench capacitor more closely to the transistor, since the transistor is not damaged by material which is contained in the conductive trench filling.
摘要翻译：沟槽电容器形成在衬底中并且包括具有上部区域和下部区域的沟槽。绝缘套环形成在沟槽的上部区域中。沟槽的下部区域延伸穿过埋置的井。作为外部电容器电极，在沟槽的下部区域周围形成掩埋板。形成电容器电介质的电介质层对沟槽的下部区域和绝缘环进行排列。将导电沟槽填充物放入沟槽中。氮化钨的导电接触层设置在绝缘套环的上方，衬底和导电沟槽填充之间，并充当扩散阻挡层。这使得可以将沟槽电容器更靠近晶体管，因为晶体管不被包含在导电沟槽填充物中的材料损坏。

6. 发明申请

US20080026530A1 Method of forming a doped portion of a semiconductor and method of forming a transistor 失效
标题翻译：形成半导体的掺杂部分的方法和形成晶体管的方法
公开(公告)号：US20080026530A1
公开(公告)日：2008-01-31
申请号：US11493028
申请日：2006-07-26
申请人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
发明人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1045
摘要： A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
摘要翻译：形成半导体衬底的掺杂部分的方法包括：在衬底表面上限定多个突起部分，突出部分具有最小高度; 在衬底表面上提供图案层; 从预定的基板部分去除图案层的部分; 执行离子注入过程，使得离子相对于衬底表面的角度小于90°，其中离子被图案层和突出部分停止，因此预定的衬底部分被掺杂了离子; 并去除图案层。

7. 发明授权

US07618867B2 Method of forming a doped portion of a semiconductor and method of forming a transistor 失效
标题翻译：形成半导体的掺杂部分的方法和形成晶体管的方法
公开(公告)号：US07618867B2
公开(公告)日：2009-11-17
申请号：US11493028
申请日：2006-07-26
申请人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
发明人： Tobias Mono , Frank Jakubowski , Hermann Sachse , Lars Voelkel , Klaus-Dieter Morhard , Dietmar Henke
IPC分类号： H01L21/336 , H01L21/425 , H01L21/22
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1045
摘要： A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
摘要翻译：形成半导体衬底的掺杂部分的方法包括：在衬底表面上限定多个突出部分，突出部分具有最小高度; 在衬底表面上提供图案层; 从预定的基板部分去除图案层的部分; 执行离子注入过程，使得离子相对于衬底表面的角度小于90°，其中离子被图案层和突出部分停止，因此预定的衬底部分被掺杂了离子; 并去除图案层。

8. 发明申请

US20050201131A1 Method for generating an electrical contact with buried track conductors 有权
标题翻译：用于产生与埋地轨道导体电接触的方法
公开(公告)号：US20050201131A1
公开(公告)日：2005-09-15
申请号：US11124726
申请日：2005-05-09
申请人： Christoph Ludwig , Klaus-Dieter Morhard , Christoph Kutter
发明人： Christoph Ludwig , Klaus-Dieter Morhard , Christoph Kutter
IPC分类号： H01L21/60 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/02 , G11C11/42
CPC分类号： H01L27/115 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.
摘要翻译：半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。

9. 发明授权

US07122434B2 Method for generating an electrical contact with buried track conductors 有权
标题翻译：用于产生与埋地轨道导体电接触的方法
公开(公告)号：US07122434B2
公开(公告)日：2006-10-17
申请号：US11124726
申请日：2005-05-09
申请人： Christoph Ludwig , Klaus-Dieter Morhard , Christoph Kutter
发明人： Christoph Ludwig , Klaus-Dieter Morhard , Christoph Kutter
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.
摘要翻译：半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。

10. 发明授权

US07452821B2 Method for the formation of contact holes for a number of contact regions for components integrated in a substrate 有权
标题翻译：用于形成针对集成在基板中的部件的多个接触区域的接触孔的方法
公开(公告)号：US07452821B2
公开(公告)日：2008-11-18
申请号：US10479733
申请日：2002-04-18
申请人： Ulrike Gruening-Von Schwerin , Wolfgang Gustin , Klaus-Dieter Morhard
发明人： Ulrike Gruening-Von Schwerin , Wolfgang Gustin , Klaus-Dieter Morhard
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L27/10894
摘要： A method is disclosed by means of which contact holes (K1), (K2) and (K3), leading to integrated components can be produced with just one structuring mask, whereby contact holes (K1) and (K3) lead to contact regions (25e, 45e) in the substrate (5) and contact holes (K2) lead to contact regions (35c, 50c) located on layer stacks (35, 50). An auxiliary layer is used for the etching of contact holes (K1), (K2), (K3), which covers a part of the contact holes and thus serves as a selection mask. The auxiliary layer can be structured with a low-resolution lithography in comparison with the mask, such that only one single high-resolution lithography is necessary for the formation of all contact holes (K1), (K2), (K3). The method is particularly suitable for the simultaneous production of contact holes for transistors in the cell field and the logic field of a DRAM.
摘要翻译：公开了一种方法，通过该方法可以仅用一个构造掩模制造导致集成部件的接触孔（K 1），（K 2）和（K 3），由此接触孔（K 1）和（K 3）导致基板（5）中的接触区域（25e，45e）和接触孔（K 2）通向位于层叠体（35,50）上的接触区域（35c，50c）。辅助层用于蚀刻覆盖部分接触孔的接触孔（K 1），（K 2），（K 3），从而用作选择掩模。与掩模相比，辅助层可以用低分辨率光刻来构造，使得仅形成所有接触孔（K 1），（K 2），（K 3）所需的单一高分辨率光刻技术是必需的，。该方法特别适用于在单元领域和DRAM的逻辑领域同时生产晶体管的接触孔。

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