专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060005090A1 Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods 审中-公开
标题翻译：在可编程逻辑器件和相关方法中比较，选择，排序和中值滤波器
公开(公告)号：US20060005090A1
公开(公告)日：2006-01-05
申请号：US11151743
申请日：2005-06-13
申请人： Martin Langhammer , Jonah Graham
发明人： Martin Langhammer , Jonah Graham
IPC分类号： G01R31/28
CPC分类号： H03K19/17732
摘要： A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.
摘要翻译：可编程逻辑器件（PLD）包括比较选择电路。比较选择电路包括逻辑元件1至N.每个逻辑元件包括比较电路和选择器电路。比较电路比较逻辑元件的两个输入，并产生逻辑元件的比较输出信号。选择器电路响应于选择信号，提供逻辑元件的两个输入中的一个作为输出。所有逻辑元件（即，逻辑元件1至N）的选择信号构成第N逻辑元件的比较输出信号。还公开了一种中值计算装置。中值滤波器装置包括至少一个插入分类电路。所述至少一个插入分类电路对与所述插入分类电路相对应的一组输入号执行插入排序，以生成相应的分类数字集合。每个排序的数字集合包括相应的一组输入数字的中值。

2. 发明授权

US06987401B1 Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods 失效
公开(公告)号：US06987401B1
公开(公告)日：2006-01-17
申请号：US10277627
申请日：2002-10-22
申请人： Martin Langhammer , Jonah Graham
发明人： Martin Langhammer , Jonah Graham
IPC分类号： H03K19/177
CPC分类号： H03K19/17732
摘要： A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

3. 发明申请

US20230027064A1 Power Savings by Register Insertion in Large Combinational Circuits 有权
公开(公告)号：US20230027064A1
公开(公告)日：2023-01-26
申请号：US17957235
申请日：2022-09-30
申请人： Martin Langhammer , Gregg William Baeckler , Sergey Vladimirovich Gribok , Mahesh A. Iyer
发明人： Martin Langhammer , Gregg William Baeckler , Sergey Vladimirovich Gribok , Mahesh A. Iyer
IPC分类号： G06F1/06 , G06F1/3237 , H03K19/00
摘要： Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.

4. 发明授权

US09582686B1 Unique secure serial ID 有权
标题翻译：唯一的安全序列号
公开(公告)号：US09582686B1
公开(公告)日：2017-02-28
申请号：US11939032
申请日：2007-11-13
申请人： Martin Langhammer , Juju Joyce
发明人： Martin Langhammer , Juju Joyce
IPC分类号： G06F21/00 , G07C9/00 , G06F21/72 , G06Q20/34 , G06F21/76 , G06K19/073
CPC分类号： G06F21/72 , G06F21/76 , G06K19/07345 , G06Q20/341 , G06Q20/3558 , G06Q50/00
摘要： Methods, circuits, and apparatus are provided an FPGA user, ASIC designer, or the like the ability to program a unique ID per each circuit into a memory, such as a non-volatile one-time programmable memory bank on an FPGA. This unique ID is secure such that no one else can replicate it on another part, thus keeping it unique to the user for which it was intended. An encryption engine receives plaintext and produces the unique ID that is stored in memory that is designed to only be writeable through the encryption engine. Thus, the FPGA/ASIC designer can track who is the customer they sold this part to or who the last authorized user is.
摘要翻译：方法，电路和装置为FPGA用户，ASIC设计者等提供将每个电路的唯一ID编程到诸如FPGA上的非易失性一次可编程存储器之类的存储器中的能力。这个唯一的ID是安全的，使得没有其他人可以在另一部分上复制它，因此保持其对于其所期望的用户是唯一的。加密引擎接收明文，并产生存储在存储器中的唯一ID，该唯一ID被设计为只能通过加密引擎写入。因此，FPGA / ASIC设计人员可以跟踪谁销售这部分的客户是谁或最后授权的用户是谁。

5. 发明授权

US08886695B1 Normalization of floating point operations in a programmable integrated circuit device 有权
标题翻译：可编程集成电路器件中浮点运算的归一化
公开(公告)号：US08886695B1
公开(公告)日：2014-11-11
申请号：US13545405
申请日：2012-07-10
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/38
CPC分类号： G06F7/49936 , G06F7/4876
摘要： A programmable integrated circuit device is programmed to normalize multiplication operations by examining the input or output values to determined the likelihood of overflow or underflow and then to adjust the input or output values accordingly. The examination of the inputs can include an examination of the number of adder stages feeding into the inputs, as well as a count of leading bits ahead of the first significant bit. Adjustment of an input can include shifting the mantissa by the leading bit count and adjusting the exponent accordingly, while adjustment of the output can include shifting the mantissa by the sum of the leading bit counts of the inputs and adjusting the exponent accordingly. Or the output can be examined to find its leading bit count and the output then can be adjusted by shifting the mantissa by the leading bit count and adjusting the exponent accordingly.
摘要翻译：可编程集成电路器件被编程为通过检查输入或输出值来归一化乘法运算，以确定溢出或下溢的可能性，然后相应地调整输入或输出值。对输入的检查可以包括对馈入馈入的加法器级数的检查以及在第一有效位之前的前导位的计数。输入的调整可以包括将尾数移位前导位数并相应地调整指数，而输出的调整可以包括将尾数移位输入的前导位计数之和并相应地调整指数。或者可以检查输出以查找其前导位计数，然后可以通过将尾数移位前导位计数并相应地调整指数来调整输出。

6. 发明授权

US08862650B2 Calculation of trigonometric functions in an integrated circuit device 有权
标题翻译：集成电路设备中三角函数的计算
公开(公告)号：US08862650B2
公开(公告)日：2014-10-14
申请号：US13288685
申请日：2011-11-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/38 , G06F7/548 , G06F1/03 , G06F1/035 , G06F7/483
CPC分类号： G06F7/548 , G06F1/03 , G06F1/035 , G06F7/483 , G06F2101/04
摘要： Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits of the input value, and circuitry for combining the first intermediate tangent value and the second intermediate tangent value to yield the tangent function of the input value.
摘要翻译：用于计算输入值的切线函数的电路包括第一查询表电路，其存储有限数量的采样值的预先计算的切线值，用于输入最重要的输入值的位的电路用作第一查找表的输入，查找预先计算的正切值中的一个作为第一中间切线值的电路，用于从输入值的剩余位的一个或多个范围计算第二中间切线值的电路，以及用于组合第一中间切线值和第二中间切线值，以产生输入值的切线函数。

7. 发明授权

US08812819B1 Methods and apparatus for reordering data signals in fast fourier transform systems 有权
标题翻译：用于在快速傅里叶变换系统中重新排序数据信号的方法和装置
公开(公告)号：US08812819B1
公开(公告)日：2014-08-19
申请号：US13212377
申请日：2011-08-18
申请人： Martin Langhammer , Kellie Marks
发明人： Martin Langhammer , Kellie Marks
IPC分类号： G06F12/00
CPC分类号： G06F17/142
摘要： Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.
摘要翻译：通过基数4n2m快速傅立叶变换（“FFT”）操作输出的数据信号项可能不符合进一步使用这些数据项所需的顺序（例如，它们可以以非自然的顺序而不是以期望的自然顺序输出订购）。存储器电路（例如，双端口存储器电路）可以与电路一起使用，该电路用于以对于每个连续的N个数据项集合的特定方式重新排序的地址信号来寻址存储器电路。这允许使用存储器电路与数据项存储位置相比，否则将重新排序数据项从非自然顺序到自然顺序。特别地，存储器电路仅需要能够在任何一个时间存储N个数据项，这比其他情况下更有效的存储器利用。

8. 发明授权

US08788562B2 Large multiplier for programmable logic device 有权
标题翻译：可编程逻辑器件的大倍数
公开(公告)号：US08788562B2
公开(公告)日：2014-07-22
申请号：US13042700
申请日：2011-03-08
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译：可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。

9. 发明授权

US08645712B1 Electronic circuit design copy protection 有权
标题翻译：电子电路设计复制保护
公开(公告)号：US08645712B1
公开(公告)日：2014-02-04
申请号：US11261155
申请日：2005-10-27
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H04L9/14
CPC分类号： H04L9/0841 , H04L9/0866 , H04L9/0869 , H04L2209/605
摘要： An electronic device takes the form of a programmable logic device, including logic resources whose functions and interconnections are dependent on the configuration information applied to the device. Each such electronic device is provided with a unique identifier. In order to implement a design of an electronic circuit on an electronic device, the configuration information that is required to cause the device to perform its desired function is encrypted before being applied to the device, and is decrypted on the device itself. The encryption process, and hence the required decryption, are based on the identifier, and hence are effectively unique to the particular device, so that the intended design can be implemented only by means of configuration information that is related to the unique identifier, and the configuration information cannot be applied to other devices to make unauthorized configured devices.
摘要翻译：电子设备采用可编程逻辑器件的形式，包括其功能和互连取决于应用于器件的配置信息的逻辑资源。每个这样的电子设备被提供有唯一的标识符。为了在电子设备上实现电子电路的设计，使得设备执行其所需功能所需的配置信息在应用于设备之前被加密，并且在设备本身上被解密。加密过程，因此所需的解密基于标识符，因此对于特定设备是有效的，因此预期的设计只能通过与唯一标识符相关的配置信息来实现，并且配置信息不能应用于其他设备进行未经授权的配置设备。

10. 发明授权

US08621331B1 Continuous parallel cyclic BCH decoding architecture 有权
公开(公告)号：US08621331B1
公开(公告)日：2013-12-31
申请号：US13152438
申请日：2011-06-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03M13/00
CPC分类号： H03M13/152 , H03M13/1545 , H03M13/6561
摘要： Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式