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1. 发明授权

US07032061B2 Multimaster bus system 有权
公开(公告)号：US07032061B2
公开(公告)日：2006-04-18
申请号：US10198572
申请日：2002-07-18
申请人： Martin Huch , Jörg Müller
发明人： Martin Huch , Jörg Müller
IPC分类号： G06F15/173 , G06F13/00
CPC分类号： G06F13/4022
摘要： A multimaster bus system includes a bus for connecting to devices connected thereto and a bus controller that controls the bus and/or the bus grant. The multimaster bus system includes providing the bus with data and/or signals paths. The bus controller can alter statically and/or dynamically the course of these paths. Such a multimaster bus system enables several connections to be simultaneously established in the easiest possible way and between the devices connected thereto.

2. 发明授权

US06412037B1 Interface configuration for connecting different types of busses to a peripheral bus 有权
标题翻译：将不同类型的总线连接到外围总线的接口配置
公开(公告)号：US06412037B1
公开(公告)日：2002-06-25
申请号：US09195485
申请日：1998-11-18
申请人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
发明人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： An interface is connected between a bus system and a unit which is to respond through the bus system. The interface is constructed for the simultaneous connection of different types of bus systems. As a result, the interface can cooperate optimally with the units that use it, even when it is used, or is to be capable of being used, by a plurality of units.
摘要翻译：一个接口连接在一个总线系统和一个要通过总线系统响应的单元之间。该接口构建用于同时连接不同类型的总线系统。结果，即使在使用时，也可以使用多个单元，能够与使用该单元的单元进行最佳配合。

3. 发明授权

US07061933B2 Multiplexer bus with local bus nodes 有权
公开(公告)号：US07061933B2
公开(公告)日：2006-06-13
申请号：US09954413
申请日：2001-09-17
申请人： Martin Huch
发明人： Martin Huch
IPC分类号： H04L12/66
CPC分类号： H04L12/44 , H04L12/40
摘要： The invention relates to a multiplexer bus comprising local bus nodes. In order to connect a plurality of transmitting-receiving circuits, the latter are connected to locally distributed bus nodes which, in turn, can be connected to additional transmitting-receiving circuits or to bus nodes. The bus nodes contain a first circuit for relaying a data signal if a control signal is transmitted in parallel with the data signal, and a second circuit for relaying the control signal.

4. 发明授权

US06421770B1 Buffer memory configuration having a memory between a USB and a CPU 失效
标题翻译：具有在USB和CPU之间的存储器的缓冲存储器配置
公开(公告)号：US06421770B1
公开(公告)日：2002-07-16
申请号：US09120160
申请日：1998-07-21
申请人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
发明人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
IPC分类号： G06F1202
CPC分类号： G06F5/16 , G06F5/10
摘要： The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory itself. The first half of the memory defines a first memory page and the second half of the memory defines a second memory page, and each address in the address space is assigned exactly one memory location on each of the memory pages. A memory management unit generates a first significant bit which assigns in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page. The buffer memory architecture enables the memory independently to manage the data to be transferred. The two memory pages serve to decouple the central processing unit CPU and the bus. Both memory pages are virtually visible to the user but only one of the memory pages can ever be addressed for data transfer. Consequently, overlapping of the writing cycles is avoided by arranging the transmitted data and the data to be read out in separate areas of the memory.
摘要翻译：缓冲存储器配置具有设置在USB和中央处理单元之间的存储器。存储器可以被映射到正好与存储器本身一半一样大的地址空间。存储器的前半部分定义第一存储器页面，并且存储器的第二半部分定义第二存储器页面，并且每个存储器页面上分配地址空间中的每个地址恰好一个存储器位置。存储器管理单元产生第一有效位，其在每种情况下将具有相同地址的两个存储器位置分配给第一存储器页的地址空间和第二存储器页的地址空间。缓冲存储器架构使内存独立地管理要传输的数据。两个存储器页面用于去耦中央处理单元CPU和总线。两个内存页面对用户实际上是可见的，但只有一个内存页面可以被寻址用于数据传输。因此，通过将发送的数据和要在存储器的不同区域中读出的数据进行布置来避免写入周期的重叠。

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