专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06646580B2 Digital/analog converter with programmable gain 有权
标题翻译：带可编程增益的数字/模拟转换器
公开(公告)号：US06646580B2
公开(公告)日：2003-11-11
申请号：US10012009
申请日：2001-10-29
申请人： Martin Clara , Hubert Weinberger , Christian Fleischhacker , Andreas Wiesbauer
发明人： Martin Clara , Hubert Weinberger , Christian Fleischhacker , Andreas Wiesbauer
IPC分类号： H03M100
CPC分类号： H03M1/66
摘要： Digital/analog converter with programmable gain for converting a digital input signal (Dn) into an analog output signal, the digital/analog converter (1) having: a signal input (2) for applying the digital input signal (Dn) a reference current source (7) for generating a reference current (Iref&phgr;), the current intensity of the reference current output by the reference current source (7) being adjustable via a setting terminal (4) of the digital/analog converter (1) current mirror circuits which mirror the generated reference current (Iref) with an associated current mirror ratio to form mirror currents a controllable switching device (57), which switches through the mirror currents output by the current mirror circuits, in a manner dependent on the digital input signal (Dn) present at the signal input (2), to a summation current node (62) for generating a summation current (Isum) and a current/voltage converter (17) for converting the generated summation current (Isum) into a corresponding voltage (UA), which is output as an analog output signal via an analog signal output (3) of the digital/analog converter (1).
摘要翻译：具有用于将数字输入信号（Dn）转换为模拟输出信号的可编程增益的数字/模拟转换器，所述数/模转换器（1）具有：用于施加数字输入信号（Dn）的信号输入（2）用于产生参考电流（Irefphi）的源（7），由参考电流源（7）输出的参考电流的电流强度可经由数字/模拟转换器（1）的设置端子（4）调节，电流镜像电路其以相关联的电流镜像比来反映所产生的参考电流（Iref），以形成镜像电流。可控开关器件（57）以取决于数字输入信号（Dn）的方式切换由电流镜电路输出的镜电流）存在于用于产生求和电流（Isum）的和电流节点（62）和用于将产生的求和电流（Isum）转换成相应的电流/电压转换器（17）的电流/电压转换器（17）电压（UA），通过数/模转换器（1）的模拟信号输出（3）作为模拟输出信号输出。

2. 发明授权

US06879273B2 Oversampling in analog/digital and digital/analog converters 有权
标题翻译：模拟/数字和数字/模拟转换器中的过采样
公开(公告)号：US06879273B2
公开(公告)日：2005-04-12
申请号：US10669280
申请日：2003-09-23
申请人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
发明人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
IPC分类号： H03M1/00 , H03M1/20 , H03M1/66 , H03M3/00 , H04B14/04 , H04B14/06
CPC分类号： H03M1/66 , H03M1/201 , H03M3/33 , H03M3/458 , H03M3/50
摘要： The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.
摘要翻译：本发明创建了一种用于数字传输模拟信号的方法和装置，其中在模拟/数字和数字/模拟转换器中执行过采样。在这种布置中，执行数字/模拟转换，其特别适用于VDSL系统。传输的数字传输信号（110）被提供给混合单元（201）并且在混合单元（201）中，施加到接收噪声源终端（209）的接收噪声信号（211）被叠加在数字传输信号（110）。与随后的噪声整形装置（205）组合的内插滤波器单元（203）提供频率带宽的增加，从而导致合适的过采样。

3. 发明授权

US06496128B2 Sigma-delta analog-to-digital converter array 有权
公开(公告)号：US06496128B2
公开(公告)日：2002-12-17
申请号：US10001022
申请日：2001-11-02
申请人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
发明人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
IPC分类号： H03M300
CPC分类号： H03M3/416
摘要： A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta modulators. The sigma-delta analog-to-digital converter array is preferably a third order device and supplies a digital output signal corresponding to a sigma-delta converter with 7-bit quantization. To this end, a second order sigma-delta modulator with 3-bit quantization and a first order sigma-delta modulator with 5-bit quantization may be used.

4. 发明授权

US07084677B2 Line driver 失效
标题翻译：线路驱动程序
公开(公告)号：US07084677B2
公开(公告)日：2006-08-01
申请号：US10788667
申请日：2004-02-27
申请人： Thomas Ferianz , Christian Fleischhacker , Dario Giotta , Rüdiger Koban , Thomas Pötscher , Andreas Wiesbauer
发明人： Thomas Ferianz , Christian Fleischhacker , Dario Giotta , Rüdiger Koban , Thomas Pötscher , Andreas Wiesbauer
IPC分类号： H03K3/00
CPC分类号： H04L25/0286 , H04L25/0266
摘要： The invention relates to a line driver arrangement for driving signals via at least one subscriber line, provided with: an input for injecting an input signal and having an output at which a signal which is to be driven via the subscriber line can be tapped off, a digital amplifier which produces a pulse-width-modulated signal on the output side from the input signal or from a signal derived from it, an analog amplifier, which produces an analog signal on the output side from the input signal or from a signal derived from it, with the outputs of the amplifiers being coupled such that the signal to be driven results from superimposition of the analog signal and the digital signal, with the gain of the analog amplifier being matched to the gain of the digital amplifier such that scatter and/or overshoot on the digital signal are at least reduced after the superimposition.
摘要翻译：本发明涉及一种用于经由至少一个用户线驱动信号的线路驱动器装置，该线路驱动器装置具有：用于注入输入信号的输入端，并且具有能够通过用户线路驱动的信号的输出，数字放大器，其在输入侧从输入信号或从其输出的信号产生脉宽调制信号，模拟放大器，其在输入侧从输入信号或从所导出的信号产生模拟信号由此，放大器的输出被耦合，使得待驱动的信号由模拟信号和数字信号的叠加产生，模拟放大器的增益与数字放大器的增益匹配，使得散射和 /或数字信号上的过冲至少在叠加后减小。

5. 发明授权

US07642877B2 Self-oscillating modulator and method for adjusting a self-oscillating modulator 有权
标题翻译：自振荡调制器和调节自振荡调制器的方法
公开(公告)号：US07642877B2
公开(公告)日：2010-01-05
申请号：US11517640
申请日：2006-09-08
申请人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
发明人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03F3/2171
摘要： A self-oscillating pulse-width modulator comprises an input, an output and a control loop. The control loop comprises a forward branch and a feedback loop. The forward branch is connected between the input and the output and comprises a comparator and a delay element. The feedback loop loops back to the input a feedback signal which depends on an output signal present at the output. The phase shift of the open control loop is 180° at the frequency of an oscillation to be generated by the modulator. At least a part of the phase shift is realized in the forward branch by means of the at least one delay element.
摘要翻译：自振荡脉冲宽度调制器包括输入，输出和控制环路。控制回路包括正向分支和反馈回路。正向分支连接在输入和输出之间，包括比较器和延迟元件。反馈环路回馈到输入端，反馈信号取决于输出端存在的输出信号。在由调制器产生的振荡频率下，开路控制环路的相移为180°。通过至少一个延迟元件在正向分支中实现至少一部分相移。

6. 发明授权

US07486214B1 Tuning methods for loop-filters of continuous-time sigma-delta modulators 有权
标题翻译：连续时间Σ-Δ调制器的环路滤波器的调谐方法
公开(公告)号：US07486214B1
公开(公告)日：2009-02-03
申请号：US11850000
申请日：2007-09-04
申请人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
发明人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/458
摘要： Techniques for tuning filters of modulation circuits are described herein.
摘要翻译：本文描述了用于调谐电路的调谐滤波器的技术。

7. 发明授权

US07576670B2 Sigma-delta analog-digital converter for an xDSL multistandard input stage 失效
标题翻译：用于xDSL多标准输入级的Sigma-delta模数转换器
公开(公告)号：US07576670B2
公开(公告)日：2009-08-18
申请号：US11661627
申请日：2004-09-02
申请人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
发明人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03M3/394 , H03M3/406 , H03M3/424 , H03M3/452
摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.
摘要翻译：本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b）其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1）以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号。

8. 发明授权

US07532082B2 Synchronization circuit for synchronizing PWM modulators 有权
标题翻译：用于同步PWM调制器的同步电路
公开(公告)号：US07532082B2
公开(公告)日：2009-05-12
申请号：US11593235
申请日：2006-11-06
申请人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
发明人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03F3/2173 , H03K5/135
摘要： A synchronization circuit for synchronizing at least two self-oscillating PWM modulators, each outputting a respective pulse-width-modulated output signal comprising signal pulses with signal pulse centers, shifts the timings of the signal pulses relative to one another such that their signal pulse centers are in sync.
摘要翻译：同步电路，用于同步至少两个自激振荡PWM调制器，每个自振荡PWM调制器输出包括具有信号脉冲中心的信号脉冲的相应的脉冲宽度调制输出信号，使信号脉冲相对于彼此的定时偏移，使得它们的信号脉冲中心正在同步

9. 发明授权

US07379005B2 Apparatus and method for spectrally shaping a reference clock signal 有权
标题翻译：对参考时钟信号进行频谱整形的装置和方法
公开(公告)号：US07379005B2
公开(公告)日：2008-05-27
申请号：US11516383
申请日：2006-09-06
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
IPC分类号： H03M1/66
CPC分类号： H03L7/08 , H03L7/18 , H03M3/372 , H03M3/464
摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).
摘要翻译：用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18）第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

10. 发明申请

US20080100342A1 Circuit arrangement comprising a level shifter and method 有权
标题翻译：电路装置包括电平转换器和方法
公开(公告)号：US20080100342A1
公开(公告)日：2008-05-01
申请号：US11546009
申请日：2006-10-11
申请人： Benno Muhlbacher , Andreas Wiesbauer , Martin Clara , Dieter Draxelmayr
发明人： Benno Muhlbacher , Andreas Wiesbauer , Martin Clara , Dieter Draxelmayr
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A circuit arrangement includes a first level shifter, an output stage, and a feedback circuit. The first level shifter is coupled to receive an input signal having a first voltage level from an input terminal, and is configured to provide a level-shifted signal having a second voltage level higher than the first voltage level. The output stage includes a first transistor that has a control terminal operably coupled to an output of the first level shifter. The output stage is configured to provide at an output terminal of the output stage an output signal based on the level-shifted signal. The feedback circuit is configured to feed back the output signal to the output of the first level shifter.
摘要翻译：电路装置包括第一电平移位器，输出级和反馈电路。第一电平移位器被耦合以从输入端子接收具有第一电压电平的输入信号，并且被配置为提供具有高于第一电压电平的第二电压电平的电平移位信号。输出级包括具有可操作地耦合到第一电平移位器的输出的控制端的第一晶体管。输出级被配置为在输出级的输出端提供基于电平移位信号的输出信号。反馈电路被配置为将输出信号反馈到第一电平移位器的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式