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    • 2. 发明授权
    • BI-CMOS integrated circuit
    • BI-CMOS集成电路
    • US06943413B2
    • 2005-09-13
    • US10428592
    • 2003-05-01
    • Steven S. Lee
    • Steven S. Lee
    • H01L21/8249H01L29/76
    • H01L21/8249
    • The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.
    • 本发明涉及一种BI-CMOS工艺,其中在公共衬底上制造场效应晶体管(FET)和双极结晶体管(BJT)。 在几个处理步骤中,与BJT结构同时形成FET结构。 例如,在一个步骤中,同时形成用于BJT的用于FET的多晶硅栅电极和多晶硅发射极。 在本发明的另一方面,多晶硅层用于减少否则在植入步骤期间会发生的沟道化。
    • 3. 发明授权
    • Method of fabricating a bipolar integrated structure
    • 制造双极一体化结构的方法
    • US5904535A
    • 1999-05-18
    • US748969
    • 1996-11-13
    • Steven S. Lee
    • Steven S. Lee
    • H01L21/8249H01L21/84H01L27/12H01L21/331
    • H01L21/84H01L21/8249H01L27/1203
    • A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.
    • 一种用于在绝缘体上硅衬底上制造双极晶体管的工艺,其包括将双极晶体管区域蚀刻到衬底中,其中双极晶体管区域具有基本垂直的侧壁和底部,并且在双极晶体管的底部形成掩埋集电极 区。 多晶硅侧壁形成在双极晶体管区域中与垂直侧壁相邻,其中多晶硅侧壁连接到埋地集电器。 多晶硅侧壁被氧化以形成氧化多晶硅层。 在氧化的多晶硅侧壁上形成氧化物侧壁,并且形成外延硅以填充双极晶体管区域。 在外延阻挡层内为双极晶体管形成基极和发射极。
    • 7. 发明授权
    • Multiple key array
    • 多重键阵列
    • US5534860A
    • 1996-07-09
    • US236797
    • 1994-05-02
    • Joseph E. PhillipsJohn J. OskorepSteven S. Lee
    • Joseph E. PhillipsJohn J. OskorepSteven S. Lee
    • H03M11/20H03M11/24
    • H03M11/24H03M11/20
    • An apparatus for and method of scanning a key array (101-116) uses two or three scan lines (134 and 135 or 308, 309, and 310), thereby limiting the need for an excessive number of input/output lines of a processor (136). A separate resistor ladder (301,302, 303) is provided for each dimension of keys, including row, column, and/or matrix. A minimal number of parts is also required to implement the resistor ladder (301,302, 303). A reference conductor (311), a row conductor (312), a column conductor (313), and, if desired, a matrix conductor (314) each run under each key, such that when a different key is depressed, a unique combination of voltages appears at the scan lines (134 and 135 or 308, 309, and 310) for the resistor ladders (301, 302, 303).
    • 用于扫描键阵列(101-116)的装置和方法使用两条或三条扫描线(134和135或308,309和310),从而限制对处理器的输入/输出线数量过多的需要 (136)。 为每个尺寸的键提供单独的电阻梯(301,302,303),包括行,列和/或矩阵。 实现电阻梯(301,302,303)也需要最少数量的部件。 参考导体(311),行导体(312),列导体(313)以及如果需要的话,每个键下的矩阵导体(314),使得当按下不同的键时,独特的组合 的电压出现在电阻梯(301,302,303)的扫描线(134和135或308,309和310)处。