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1. 发明授权

US08386688B2 Modular integrated circuit with common interface 失效
公开(公告)号：US08386688B2
公开(公告)日：2013-02-26
申请号：US12770690
申请日：2010-04-29
申请人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
发明人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F1/10 , G06F1/26 , G06F13/4027 , G06F2213/0038 , Y02D30/34
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

2. 发明申请

US20110271028A1 MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE 失效
标题翻译：具有通用接口的模块化集成电路
公开(公告)号：US20110271028A1
公开(公告)日：2011-11-03
申请号：US12770690
申请日：2010-04-29
申请人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
发明人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
IPC分类号： G06F13/36 , G06F1/24
CPC分类号： G06F13/28 , G06F1/10 , G06F1/26 , G06F13/4027 , G06F2213/0038 , Y02D30/34
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。所述多个集线器接口在所述集线器模块和所述多个辐条模块中的每一个之间提供多个信号接口，其中所述多个信号接口中的每一个与所述多个信号接口中的每一个信号接口隔离，并且其中多个信号接口中的每一个根据公共信令格式进行操作。

3. 发明申请

US20110276766A1 CONFIGURABLE MEMORY CONTROLLER 审中-公开
标题翻译：可配置内存控制器
公开(公告)号：US20110276766A1
公开(公告)日：2011-11-10
申请号：US12774462
申请日：2010-05-05
申请人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
发明人： Mark N. Fullerton , Sathish Kumar Radhakrishnan , Brent Mulholland , Ravi S. Setty , Lance Flake , Vinay Bhasin
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3215 , G06F13/1626 , H04W52/0274 , Y02D10/13 , Y02D10/14 , Y02D70/142 , Y02D70/144
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译：控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。然后将最高排名的客户端传递给定序器以允许请求的访问。时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。处理通过相关的逻辑电路并行（同时）在硬件中执行。

4. 发明申请

US20080170685A1 Data scrambling circuit 审中-公开
标题翻译：数据加扰电路
公开(公告)号：US20080170685A1
公开(公告)日：2008-07-17
申请号：US11655685
申请日：2007-01-19
申请人： Lance Flake , Brent Mulholland
发明人： Lance Flake , Brent Mulholland
IPC分类号： H04L9/28
CPC分类号： G11B20/00086 , G06F21/72 , G11B20/0021 , G11B2020/1843 , G11B2220/2516
摘要： A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.
摘要翻译：提供数据加扰电路。数据加扰电路包括具有数字逻辑器件和耦合到数字逻辑器件的接口电路的集成电路。还包括耦合到接口电路上的输出引脚的外部存储器。数字逻辑器件将图形数据传送到接口电路。然后，接口电路对图形化数据进行加扰，以产生要存储在外部存储器内的伪随机输出，并从外部存储器解扰一个伪随机信号，以产生未被数字逻辑器件读取的未加扰数据。

5. 发明授权

US07370230B1 Methods and structure for error correction in a processor pipeline 有权
标题翻译：处理器管道中纠错的方法和结构
公开(公告)号：US07370230B1
公开(公告)日：2008-05-06
申请号：US10801209
申请日：2004-03-16
申请人： Lance Flake
发明人： Lance Flake
IPC分类号： G06F11/00
CPC分类号： G06F11/1008
摘要： Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correction stages to correct a soft error using the fetched unit of information and the associated error correcting codes. By extending the pipeline, soft error correction does not stall the pipeline and hence system performance is improved in the face of soft errors from an error correcting memory subsystem.
摘要翻译：改进的处理器管道的方法和结构，以消除可纠正的软错误对处理器/存储器管线性能的影响。其特征和方面提供了通过添加一个或多个信息校正阶段来扩展流水线，以使用获取的信息单元和相关联的纠错码来校正软错误。通过扩展流水线，软错误校正不会阻碍流水线，因此面对来自纠错存储器子系统的软错误，系统性能得到改善。

6. 发明授权

US07818629B2 Multiple winner arbitration 失效
标题翻译：多次获胜仲裁
公开(公告)号：US07818629B2
公开(公告)日：2010-10-19
申请号：US11866638
申请日：2007-10-03
申请人： Lance Flake
发明人： Lance Flake
IPC分类号： G06F11/00
CPC分类号： G06F11/3495 , G06F11/3485 , G11B27/36
摘要： A method to combine trace data for multiple systems within an embedded system is provided. This method involves coupling a set of trace sources within the embedded system to a trace system. A subset of trace source(s) may then be selected from the set of trace sources. The subset of trace sources may be formatted to produce a packetized trace stream. The packetized trace stream may then be provided to external interface circuitry. External circuitry coupled to the trace system allows for analysis of the packetized trace streams regarding internal operations within the embedded system. An arbitrator may determine which trace source(s) from the set of trace sources are selected to be within the subset of trace sources. The arbitrator may use several criteria to make this determination.
摘要翻译：提供了一种在嵌入式系统中组合多个系统的跟踪数据的方法。该方法涉及将嵌入式系统中的一组跟踪源耦合到跟踪系统。然后可以从该组跟踪源中选择跟踪源的子集。跟踪源的子集可以被格式化以产生分组跟踪流。然后可以将打包的跟踪流提供给外部接口电路。耦合到跟踪系统的外部电路允许关于嵌入式系统内部操作的分组化跟踪流的分析。仲裁员可以确定来自该组跟踪源的哪些跟踪源被选择在跟踪源的子集内。仲裁员可以使用几个标准来做出这一决定。

7. 发明申请

US20080005457A1 Disk controller, channel interface and methods for use therewith 失效
标题翻译：磁盘控制器，通道接口及其使用方法
公开(公告)号：US20080005457A1
公开(公告)日：2008-01-03
申请号：US11444821
申请日：2006-06-01
申请人： Lance Flake , John P. Mead
发明人： Lance Flake , John P. Mead
IPC分类号： G06F12/00
CPC分类号： G06F3/0635 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0674 , G11B5/59688 , Y02D10/154
摘要： A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.
摘要翻译：通道接口将通道电路耦合到盘驱动器的控制器电路，通道电路包括通道寄存器，并且控制器电路包括用于执行读取和写入命令的控制器寄存器。通道接口包括在控制器电路和通道电路之间的双向传输路径，其可操作以传送磁盘读取数据和磁盘写入数据，以提供控制器电路对通道寄存器的读取和写入的访问，并提供通道电路访问从控制器寄存器读取和写入。通道接口还包括控制器电路和通道电路之间的第一单向传输路径，其可操作以将伺服数据从通道电路传送到控制器电路。

8. 发明授权

US07587538B2 Disk controller, channel interface and methods for use therewith 失效
标题翻译：磁盘控制器，通道接口及其使用方法
公开(公告)号：US07587538B2
公开(公告)日：2009-09-08
申请号：US11444821
申请日：2006-06-01
申请人： Lance Flake , John P. Mead
发明人： Lance Flake , John P. Mead
IPC分类号： G06F13/12
CPC分类号： G06F3/0635 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0674 , G11B5/59688 , Y02D10/154
摘要： A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.
摘要翻译：通道接口将通道电路耦合到盘驱动器的控制器电路，通道电路包括通道寄存器，并且控制器电路包括用于执行读取和写入命令的控制器寄存器。通道接口包括在控制器电路和通道电路之间的双向传输路径，其可操作以传送磁盘读取数据和磁盘写入数据，以提供控制器电路对通道寄存器的读取和写入的访问，并提供通道电路访问从控制器寄存器读取和写入。通道接口还包括控制器电路和通道电路之间的第一单向传输路径，其可操作以将伺服数据从通道电路传送到控制器电路。

9. 发明申请

US20080005749A1 Hard disk controller having multiple, distributed processors 审中-公开
标题翻译：具有多个分布式处理器的硬盘控制器
公开(公告)号：US20080005749A1
公开(公告)日：2008-01-03
申请号：US11444583
申请日：2006-06-01
申请人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
发明人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
IPC分类号： G06F9/46
CPC分类号： G06F3/0658 , G06F3/061 , G06F3/0676
摘要： Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.
摘要翻译：具有多个分布式处理器的硬盘控制器。提出了一种新颖的方法，通过该方法提供单独的专用处理器来为硬盘驱动器（HDD）控制器内的多个控制环路中的每一个提供服务。例如，实现第一处理器以服务伺服控制环路，实施第二处理器来服务信道接口，并且第三处理器被实现为服务主机接口。在一些实施例中，使用分别在盘管理器模块和主机管理器模块中实现的协议处理器来执行信道和主机接口。

10. 发明申请

US20070033493A1 Using fractional sectors for mapping defects in disk drives 有权
$Using fractional sectors for mapping defects in disk drives$
标题翻译：使用分数扇区来映射磁盘驱动器中的缺陷
公开(公告)号：US20070033493A1
公开(公告)日：2007-02-08
申请号：US11187580
申请日：2005-07-22
申请人： Lance Flake
发明人： Lance Flake
IPC分类号： G11C29/00
CPC分类号： G11B20/18 , G11B2020/1826 , G11B2020/1896 , G11B2220/2516 , G11C29/76
摘要： Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.
摘要翻译：这里描述了至少一种用于当使用一个或多个分数扇区映射一个或多个缺陷时处理读取或写入操作的方法和系统。该方法包括使用一个或多个分数扇区来映射缺陷并存储数据符号。此外，第一算法用于将逻辑块地址转换为物理起始位置，使得可以在读取或写入操作期间处理一个或多个分数扇区。第二种算法用于在时间上处理磁盘驱动器的磁道的一个或多个部分，其中一个或多个部分可以包括一个或多个缺陷分数扇区，无缺陷分数扇区，帧余数和伺服扇区。该系统包括驻留在所述存储器中的存储器，处理器和软件。该过程执行实现第一和第二算法的软件。

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