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1. 发明申请

US20080005384A1 Hard disk drive progressive channel interface 审中-公开
标题翻译：硬盘驱动器逐行通道接口
公开(公告)号：US20080005384A1
公开(公告)日：2008-01-03
申请号：US11444584
申请日：2006-06-01
申请人： John P. Mead , Lance Flake
发明人： John P. Mead , Lance Flake
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F3/0601 , G06F2003/0697 , G11B20/1833 , G11B2020/1863 , G11B2220/2516
摘要： Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented within a hard disk drive (HDD). Because of the location in which the disk management operations are supported and performed within the channel circuitry, the interface between the channel circuitry and the controller circuitry can be implemented to support direct memory access (DMA) protocol data transfers and control there between. Because the disk management operations are supported within the channel circuitry, as opposed to the controller circuitry, then the disk management operations need not necessarily comply with an interface between the channel circuitry and the controller circuitry. This allows for better control of the disk management operations as well as a much broader range and type of interface that can be employed for the interface between the two circuitries.
摘要翻译：硬盘驱动器逐行通道接口。提出了一种新颖的方法，通过该方法，通道电路和控制器电路之间的接口，例如可以在硬盘驱动器（HDD）内实现的接口。由于在通道电路内支持和执行磁盘管理操作的位置，可以实现通道电路和控制器电路之间的接口，以支持直接存储器访问（DMA）协议数据传输和控制。由于在通道电路中支持磁盘管理操作，与控制器电路相反，因此磁盘管理操作不必一定符合通道电路和控制器电路之间的接口。这允许更好地控制磁盘管理操作以及可以用于两个电路之间的接口的更广泛的范围和类型的接口。

2. 发明申请

US20080005457A1 Disk controller, channel interface and methods for use therewith 失效
标题翻译：磁盘控制器，通道接口及其使用方法
公开(公告)号：US20080005457A1
公开(公告)日：2008-01-03
申请号：US11444821
申请日：2006-06-01
申请人： Lance Flake , John P. Mead
发明人： Lance Flake , John P. Mead
IPC分类号： G06F12/00
CPC分类号： G06F3/0635 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0674 , G11B5/59688 , Y02D10/154
摘要： A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.
摘要翻译：通道接口将通道电路耦合到盘驱动器的控制器电路，通道电路包括通道寄存器，并且控制器电路包括用于执行读取和写入命令的控制器寄存器。通道接口包括在控制器电路和通道电路之间的双向传输路径，其可操作以传送磁盘读取数据和磁盘写入数据，以提供控制器电路对通道寄存器的读取和写入的访问，并提供通道电路访问从控制器寄存器读取和写入。通道接口还包括控制器电路和通道电路之间的第一单向传输路径，其可操作以将伺服数据从通道电路传送到控制器电路。

3. 发明授权

US07587538B2 Disk controller, channel interface and methods for use therewith 失效
标题翻译：磁盘控制器，通道接口及其使用方法
公开(公告)号：US07587538B2
公开(公告)日：2009-09-08
申请号：US11444821
申请日：2006-06-01
申请人： Lance Flake , John P. Mead
发明人： Lance Flake , John P. Mead
IPC分类号： G06F13/12
CPC分类号： G06F3/0635 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0674 , G11B5/59688 , Y02D10/154
摘要： A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.
摘要翻译：通道接口将通道电路耦合到盘驱动器的控制器电路，通道电路包括通道寄存器，并且控制器电路包括用于执行读取和写入命令的控制器寄存器。通道接口包括在控制器电路和通道电路之间的双向传输路径，其可操作以传送磁盘读取数据和磁盘写入数据，以提供控制器电路对通道寄存器的读取和写入的访问，并提供通道电路访问从控制器寄存器读取和写入。通道接口还包括控制器电路和通道电路之间的第一单向传输路径，其可操作以将伺服数据从通道电路传送到控制器电路。

4. 发明申请

US20080005749A1 Hard disk controller having multiple, distributed processors 审中-公开
标题翻译：具有多个分布式处理器的硬盘控制器
公开(公告)号：US20080005749A1
公开(公告)日：2008-01-03
申请号：US11444583
申请日：2006-06-01
申请人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
发明人： John P. Mead , Lance Flake , Kevin W. McGinnis , Brent Mulholland
IPC分类号： G06F9/46
CPC分类号： G06F3/0658 , G06F3/061 , G06F3/0676
摘要： Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.
摘要翻译：具有多个分布式处理器的硬盘控制器。提出了一种新颖的方法，通过该方法提供单独的专用处理器来为硬盘驱动器（HDD）控制器内的多个控制环路中的每一个提供服务。例如，实现第一处理器以服务伺服控制环路，实施第二处理器来服务信道接口，并且第三处理器被实现为服务主机接口。在一些实施例中，使用分别在盘管理器模块和主机管理器模块中实现的协议处理器来执行信道和主机接口。

5. 发明授权

US08024637B2 Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices 有权
标题翻译：适用于包括硬盘驱动器（HDD）和其他存储器存储设备在内的通信系统的超块纠错码（ECC）
公开(公告)号：US08024637B2
公开(公告)日：2011-09-20
申请号：US11855838
申请日：2007-09-14
申请人： William Gene Bliss , Gregory L. Silvus , John P. Mead , Thomas V. Souvignier
发明人： William Gene Bliss , Gregory L. Silvus , John P. Mead , Thomas V. Souvignier
IPC分类号： H03M13/00
CPC分类号： H03M13/2966 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/258 , H03M13/2906 , H03M13/2909 , H03M13/2942 , H03M13/2957
摘要： Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.
摘要翻译：适用于包括硬盘驱动器（HDD）和其他存储器存储设备在内的通信系统的超块纠错码（ECC）。提供了一种可以组织多个信息块的装置，其中提供了一定程度的ECC，并经由信号发送到通信信道中。在一些情况下，通信信道如HDD的上下文中的那样被耦合到存储介质上，并且经由该通信信道（例如，“读取通道”）将信息写入存储介质并从存储介质读取信息。这意味着特别适用于通过任何一种传输（例如，DVR / PVR（数字/个人录像机））提供大量数据的应用。使用多个信息块中的每一个的信息生成冗余块，从而在大部分数据上提供额外的ECC，并且该冗余块也经历ECC编码。

6. 发明授权

US07900122B2 Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation 有权
标题翻译：简化RS（Reed-Solomon）码解码器，可以消除误差值多项式计算
公开(公告)号：US07900122B2
公开(公告)日：2011-03-01
申请号：US11717469
申请日：2007-03-13
申请人： Ba-Zhong Shen , John P. Mead
发明人： Ba-Zhong Shen , John P. Mead
IPC分类号： H03M13/15
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/153 , H03M13/1535 , H03M13/154 , H03M13/157 , H03M13/1585 , H03M13/6502
摘要： Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.
摘要翻译：简化RS（Reed-Solomon）码解码器，可以消除误差值多项式计算。本文提出了一种新颖的方法，其中可以直接计算误差大小（或误差值），而不需要产生误差值多项式（EVP）。在这里采用Koetter解码方法和Forney公式的修改来执行误差值的直接计算。该方法可操作以节省通常用于计算EVP的计算时钟周期，并且这些时钟周期可以用于减少ECC设计中另外需要的并行性和复杂性，这可能需要在执行分配的错误校正时间也可能导致节能。与此相关的一些优点可能包括降低风险，减少设计时间，并在整体设计中具有更高的可扩展性。

7. 发明申请

US20080168335A1 Area efficient on-the-fly error correction code (ECC) decoder architecture 审中-公开
标题翻译：区域效率即时纠错码（ECC）解码器架构
公开(公告)号：US20080168335A1
公开(公告)日：2008-07-10
申请号：US11717468
申请日：2007-03-13
申请人： John P. Mead
发明人： John P. Mead
IPC分类号： H03M13/00
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/153 , H03M13/1535 , H03M13/154 , H03M13/157 , H03M13/1585 , H03M13/6502
摘要： Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.
摘要翻译：区域效率即时纠错码（ECC）解码器架构。提供了一种中间装置，当根据里德 - 所罗门（RS）编码信号的解码产生错误位置多项式时，仅使用2组寄存器（与3个或更多个存储体相反）。当解码这样的RS编码信号时，可以采用Berlekamp-Massey解码处理。这种方法提供了大量的硬件节省。例如，根据本发明设计的一个实施例可操作以实现仅消耗大约170k个门的HDD应用的整个12位（t = 120）Reed-Solomon ECC系统。在这170公里的大门中，70K个门被归因于综合征/符号计算机。此外，由于这里呈现的解码处理的流水线布置（其允许更多的时钟周期来执行划分），因此可以使用反相器和乘法器执行分割处理。

8. 发明申请

US20080168315A1 Modified defect scan over sync mark/preamble field 有权
标题翻译：修改缺陷扫描同步标记/前导字段
公开(公告)号：US20080168315A1
公开(公告)日：2008-07-10
申请号：US11786981
申请日：2007-04-13
申请人： John P. Mead , Bahjat Zafer
发明人： John P. Mead , Bahjat Zafer
IPC分类号： G06F11/00
CPC分类号： G11B20/1803 , G01R33/1207 , G11B2020/1287
摘要： A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.
摘要翻译：一种在读取存储在盘上的缺陷扫描模式时的缺陷检测技术，其中检测到的缺陷根据缺陷驻留的扇区的哪个区域被不同地处理。在一个实现中，使用掩模来识别不同区域的缺陷。通过区分扇区内的不同区域进行缺陷扫描，可以将同步标记和前同步码字段视为关键区域，以便在执行缺陷扫描时可以归因于不同的缺陷扫描属性。

9. 发明授权

US08024640B2 Read/write channel coding and methods for use therewith 有权
标题翻译：读/写通道编码及其使用方法
公开(公告)号：US08024640B2
公开(公告)日：2011-09-20
申请号：US11923472
申请日：2007-10-24
申请人： William Gene Bliss , Bahjat Zafer , John P. Mead
发明人： William Gene Bliss , Bahjat Zafer , John P. Mead
IPC分类号： H03M13/00
CPC分类号： G11B20/10203 , G11B20/10194 , G11B20/1803 , G11B2020/1457
摘要： A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.
摘要翻译：写通道包括预编码模块，其对写入数据进行编码以产生预编码数据。纠错码（ECC）模块基于预编码数据生成ECC数据。后编码模块对ECC数据进行编码以产生后编码数据。组合模块将预编码数据和用于写入的后编码数据组合到存储介质。

10. 发明授权

US07975200B2 Error correction code (ECC) decoding architecture design using synthesis-time design parameters 失效
标题翻译：纠错码（ECC）解码架构设计采用合成时间设计参数
公开(公告)号：US07975200B2
公开(公告)日：2011-07-05
申请号：US11840606
申请日：2007-08-17
申请人： John P. Mead
发明人： John P. Mead
IPC分类号： H03M13/00
CPC分类号： G06F17/505 , H03M13/1102 , H03M13/1515 , H03M13/153 , H03M13/1535 , H03M13/6508 , H03M13/6561
摘要： Error correction code (ECC) decoding architecture design using synthesis-time design parameters. An approach is presented herein by which an ECC decoding architecture can be designed using synthesis-time design parameters. The manner presented herein allows for a designer to arrive at an ECC decoding architecture in a more direct, straightforward manner that using prior art means. A number of considerations (e.g., architecture parameters, semi-soft design constraints, parallel implementation, etc.) are initially provided; certain or all of these considerations can be predetermined, determined adaptively, and/or modified during the design process. A designer is provided a means by which a most desirable ECC decoding architecture can be arrived at relatively quickly.
摘要翻译：纠错码（ECC）解码架构设计采用合成时间设计参数。本文提出了一种使用合成时间设计参数来设计ECC解码架构的方法。本文给出的方式允许设计者以更直接，直接的方式得到使用现有技术手段的ECC解码架构。最初提供了许多考虑（例如，架构参数，半软设计约束，并行实现等）; 在设计过程中可以预先确定，确定或修改某些或所有这些因素。为设计者提供了可以相对较快地到达最理想的ECC解码架构的手段。

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