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1. 发明授权

US06418008B1 Enhanced capacitor shape 有权
标题翻译：增强电容器形状
公开(公告)号：US06418008B1
公开(公告)日：2002-07-09
申请号：US09798992
申请日：2001-03-06
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01G4005
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over-capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.
摘要翻译：提供具有梨形截面的电容器。在一个实施例中，梨形电容器是用于具有位线电容器结构的动态随机存取存储器电路中的堆叠容器电容器。每个电容器处于与所有相邻位线触点的最小位线距离，并且在与其周边的实质部分的所有相邻电容器的最小电容器距离处。

2. 发明授权

US06391709B1 Enhanced capacitor shape 有权
公开(公告)号：US06391709B1
公开(公告)日：2002-05-21
申请号：US09394401
申请日：1999-09-13
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over- capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.

3. 发明授权

US06369432B1 Enhanced capacitor shape 失效
标题翻译：增强电容器形状
公开(公告)号：US06369432B1
公开(公告)日：2002-04-09
申请号：US09028050
申请日：1998-02-23
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over- capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.
摘要翻译：提供具有梨形截面的电容器。在一个实施例中，梨形电容器是用于具有位线电容器结构的动态随机存取存储器电路中的堆叠容器电容器。每个电容器处于与所有相邻位线触点的最小位线距离，并且在与其周边的实质部分的所有相邻电容器的最小电容器距离处。

4. 发明授权

US06319644B2 Methods of reducing proximity effects in lithographic processes 有权
公开(公告)号：US06319644B2
公开(公告)日：2001-11-20
申请号：US09780407
申请日：2001-02-12
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F7/70441
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.

5. 发明授权

US06284419B1 Methods of reducing proximity effects in lithographic processes 有权
公开(公告)号：US06284419B1
公开(公告)日：2001-09-04
申请号：US09769603
申请日：2001-01-24
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F900
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.

6. 发明授权

US06238824B1 Method for designing and making photolithographic reticle, reticle, and photolithographic process 有权
标题翻译：光刻掩模版，光罩和光刻工艺的设计和制造方法
公开(公告)号：US06238824B1
公开(公告)日：2001-05-29
申请号：US09386314
申请日：1999-08-31
申请人： John R. Futrell , Christophe Pierrat , William Stanton
发明人： John R. Futrell , Christophe Pierrat , William Stanton
IPC分类号： G03F900
CPC分类号： G03F9/7003 , G03F1/36 , G03F7/70441
摘要： There are provided methods for making a reticle for use in a photolithography process, comprising generating an first reticle layout having at least one printable reticle feature, generating a modified reticle layout having the first reticle layout and at least one correction area, generating an alignment budget-containing reticle layout having at least one different printable reticle feature and at least one alignment budget border area, and removing from the modified reticle layout any area of overlap between the at least one correction area and the at least one alignment budget border area. There are also provided reticles formed according to such methods. In addition, there are provided computer-implemented methods for designing such a reticle, as well as computer readable storage media, and computer systems for use in making such reticles. In addition, there are provided photolithographic processes using such a reticle.
摘要翻译：提供了用于制造用于光刻工艺的掩模版的方法，包括产生具有至少一个可打印掩模版特征的第一掩模布局，产生具有第一掩模版布局的修改的掩模版布局和至少一个校正区域，产生对准预算具有至少一个不同的可打印标线特征和至少一个对准预算边界区域的标线布局，以及从所述修改的标线布局移除所述至少一个校正区域和所述至少一个对准预算边界区域之间的任何重叠区域。还提供根据这种方法形成的掩模版。此外，提供了用于设计这种掩模版的计算机实现的方法以及计算机可读存储介质以及用于制作这种掩模版的计算机系统。此外，提供了使用这种掩模版的光刻工艺。

7. 发明授权

US06120952A Methods of reducing proximity effects in lithographic processes 有权
标题翻译：降低光刻过程中邻近效应的方法
公开(公告)号：US06120952A
公开(公告)日：2000-09-19
申请号：US164786
申请日：1998-10-01
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/36 , G03F7/70441
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
摘要翻译：描述了将集成电路图案从掩模转印到半导体衬底上的平版印刷工艺中的邻近效应的降低方法。在一个实施例中，期望的间隔被定义在要驻留在掩模上并且要被转印到基板上的主要特征之间，以及相邻的邻近效应校正特征之间。在间隔定义之后，相对于邻近效应校正特征调整主要特征的尺寸以实现期望的转移的主要特征维度。在另一个实施例中，在具有边缘的主要特征和相邻的子分辨率特征之间限定期望的间隔。主要特征的边缘相对于子分辨率特征移动以实现所需的传送主要特征维度。

8. 发明授权

US08316326B1 System and method for applying phase effects of mask diffraction patterns 有权
$System and method for applying phase effects of mask diffraction patterns$
标题翻译：用于施加掩模衍射图案的相位效应的系统和方法
公开(公告)号：US08316326B1
公开(公告)日：2012-11-20
申请号：US12435246
申请日：2009-05-04
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G06F17/50
CPC分类号： G03F7/70125 , G03F1/70 , G03F7/70283 , G03F7/705
摘要： In accordance with some embodiments, a method is provided for creating a photolithographic component, comprising: determining a target pattern for a circuit layout, the target pattern comprising target features; identifying a set of periodic target features within the target pattern; calculating a relationship between feature and pitch for the set of periodic target features; and determining a mask pattern from the target pattern using the relationship, wherein the mask pattern has a set of periodic mask features configured to result in projection of a first subset of the set of periodic target features when exposed to a light source that induces a first phase effect, and configured to result in projection of a second subset of the set of periodic target features when exposed to a light source that induces a second phase effect. In further embodiments, the method outputs the mask pattern as a mask dataset.
摘要翻译：根据一些实施例，提供了一种用于创建光刻部件的方法，包括：确定电路布局的目标图案，所述目标图案包括目标特征; 识别目标模式内的一组周期性目标特征; 计算一组周期性目标特征的特征和音调之间的关系; 以及使用所述关系从所述目标图案确定掩模图案，其中所述掩模图案具有一组周期性掩模特征，其被配置为当暴露于引起所述第一并且被配置为当暴露于引起第二相位效应的光源时导致该组周期性目标特征的第二子集的投影。在另外的实施例中，该方法输出掩模图案作为掩码数据集。

9. 发明申请

US20110207056A1 Contact or proximity printing using a magnified mask image 审中-公开
标题翻译：使用放大掩模图像进行接触或接近打印
公开(公告)号：US20110207056A1
公开(公告)日：2011-08-25
申请号：US13066816
申请日：2011-04-25
申请人： Christophe Pierrat , Alfred Kwok-Kit Wong
发明人： Christophe Pierrat , Alfred Kwok-Kit Wong
IPC分类号： G03F7/20 , G03B27/54
CPC分类号： B82Y10/00 , G03F7/70325 , G03F7/70958
摘要： Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.
摘要翻译：集成电路制造的改进由印刷在晶片上的特征的尺寸的减小驱动。通过使用相移掩模，离轴照明和接近效应校正，目前的光刻技术限制已得到扩展。最近，已经提出液浸光刻作为进一步扩展光学光刻的限制的一种方式。本发明描述了一种基于使用投影透镜的接触或邻近打印以将掩模的图像定义到晶片上的方法。当以固体材料进行成像时，可以获得更大的折射率并且可以提高成像系统的分辨率。

10. 发明授权

US07927928B2 Spacer double patterning for lithography operations 有权
标题翻译：用于光刻操作的间隔双重图案
公开(公告)号：US07927928B2
公开(公告)日：2011-04-19
申请号：US12014985
申请日：2008-01-16
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： H01L21/335
CPC分类号： H01L21/0337
摘要： Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.
摘要翻译：公开了半导体器件制造和布局生成的系统和方法。一种示例性方法包括沉积第一材料的层并图案化该层以形成初始图案的过程，其中初始图案使用单次曝光来定义布局元件的关键特征; 在衬底上的第一图案上沉积间隔物材料并蚀刻间隔物材料，使得间隔物材料从衬底和第一图案的水平表面移除，但保持邻近第一图案的垂直表面; 在将间隔物材料留在间隔物图案中的同时从衬底去除初始图案; 用最终材料填充间隔图案; 以及修整填充图案以去除最终材料的部分超出布局元件的尺寸。

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