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1. 发明授权

US06418525B1 Method and apparatus for reducing latency in set-associative caches using set prediction 失效
标题翻译：使用集合预测减少集合关联高速缓存中的等待时间的方法和装置
公开(公告)号：US06418525B1
公开(公告)日：2002-07-09
申请号：US09240348
申请日：1999-01-29
申请人： Mark J. Charney , Philip G. Emma , Daniel A. Prener , Thomas R. Puzak
发明人： Mark J. Charney , Philip G. Emma , Daniel A. Prener , Thomas R. Puzak
IPC分类号： G06F1208
CPC分类号： G06F9/3806 , G06F9/30047 , G06F9/3814 , G06F9/3824 , G06F9/3832 , G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory and reducing power consumption. The set prediction information is stored in various locations including a branch target buffer, instruction cache and operand history table to decrease latency for accesses to set-associative instruction and data caches.
摘要翻译：一种用于存储和利用关于将被访问哪组集合关联存储器的集合预测信息以增强集合关联存储器的性能并降低功耗的方法和装置。设定的预测信息被存储在包括分支目标缓冲器，指令高速缓存和操作数历史表的各种位置中，以减少对设置关联指令和数据高速缓存的访问的等待时间。

2. 发明授权

US07441110B1 Prefetching using future branch path information derived from branch prediction 失效
标题翻译：使用从分支预测得到的未来分支路径信息进行预取
公开(公告)号：US07441110B1
公开(公告)日：2008-10-21
申请号：US09458883
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3844
摘要： A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.
摘要翻译：描述了一种机制，其预测在指令的解码周期期间预取指令的有用性。被预测为有用的预取指令（预取有用数据）被发送到处理器的执行单元用于执行，而被预测为无用的指令被丢弃。使用包含在分支历史机制中的分支预测掩模来执行关于预取指令的有用性的预测。将该掩码与包含在预取指令中的信息进行比较，该预取指令记录预取指令和数据的实际使用之间的分支路径。可以使用这种机制来预取指令和数据。

3. 发明授权

US06560693B1 Branch history guided instruction/data prefetching 失效
标题翻译：分支历史指导/数据预取
公开(公告)号：US06560693B1
公开(公告)日：2003-05-06
申请号：US09459739
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/3455 , G06F9/3836 , G06F9/3844
摘要： A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.
摘要翻译：描述了使用分支指令作为预取触发器将指令和数据预取到高速缓存中的机制。如果分支指令之后的预测执行路径与先前查看的执行路径匹配，则启动预取。使用分支历史队列确定执行路径的这种匹配，该分支历史队列记录节目中分支的分支结果（已取/未采用）。对于该队列中的每个分支，分支历史掩码记录下一个N个分支的结果，并且作为分支指令之后的执行路径的编码。分支指令与掩码一起与预取地址（指令或数据地址）相关联，并且在再次执行分支时用于触发预取。还描述了一种机制，以通过在观察到预取指令或数据的有用性之后适当地调整N的值来提高预取的及时性。

4. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

5. 发明授权

US6032245A Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads 失效
标题翻译：用于执行推测性指令线程的多处理器计算机系统中的中断处理方法和系统
公开(公告)号：US6032245A
公开(公告)日：2000-02-29
申请号：US914301
申请日：1997-08-18
申请人： Christos John Georgiou , Daniel A. Prener
发明人： Christos John Georgiou , Daniel A. Prener
IPC分类号： G06F9/48 , G06F9/30
CPC分类号： G06F9/4812
摘要： In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor. The AND operation is performed on the speculation bit and the class enable bit which corresponds to the received interrupt class, so as to determine whether that processor is included in the subset. One of the processors in the subset is selected to process the received interrupt, if the subset includes at least one processor.
摘要翻译：在多处理器系统的系统总线控制器中，提供了用于选择一个处理器来处理中断的装置。为在每个处理器上执行的每个相应任务提供掩码。每个掩码包括识别任务是否是推测性的推测位。每个掩码包括多个类允许位，用于识别该任务是否可以被与多个类使能位中的每一个相关联的相应类别的中断来中断。系统总线中的控制线接收到具有接收到的中断类的中断。识别处理器的一个子集; 子集中的处理器可以基于所接收到的中断类别以及分配给在每个相应处理器上执行的任务的相应的推测位和类使能位被中断。对与在每个处理器上执行的相应任务相关联的掩码执行布尔AND运算。在与所接收的中断类对应的推测位和类使能位上执行“与”运算，以便确定该处理器是否包括在该子集中。如果子集包括至少一个处理器，则选择该子集中的一个处理器来处理所接收的中断。

6. 发明授权

US09535694B2 Vector processing in an active memory device 有权
标题翻译：有源存储设备中的向量处理
公开(公告)号：US09535694B2
公开(公告)日：2017-01-03
申请号：US13569359
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F15/00 , G06F1/04 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括用于有源存储器设备中的向量处理的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。确定并行重复子指令执行的迭代次数。基于迭代计数，由处理元件并行地重复子指令的执行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

7. 发明授权

US5125092A Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes 失效
标题翻译：用于提供多个条件代码字段的方法和设备允许管道指令内容可以自由访问单独的条件代码
公开(公告)号：US5125092A
公开(公告)日：1992-06-23
申请号：US294850
申请日：1989-01-09
申请人： Daniel A. Prener
发明人： Daniel A. Prener
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3885
摘要： A computer system includes a condition register having multiple fields. Each field may be used as an independent condition register. A compiler which generates executable code for the computer system assigns instructions to different fields, allowing condition values to be saved while other conditions are evaluated and allowing consecutive instructions which generate or test condition values to be overlapped in their execution.

8. 发明授权

US09038040B2 Method for partitioning programs between a general purpose core and one or more accelerators 有权
标题翻译：用于在通用内核和一个或多个加速器之间划分程序的方法
公开(公告)号：US09038040B2
公开(公告)日：2015-05-19
申请号：US11339592
申请日：2006-01-25
申请人： John Kevin Patrick O'Brien , Kathryn M. O'Brien , Daniel A. Prener
发明人： John Kevin Patrick O'Brien , Kathryn M. O'Brien , Daniel A. Prener
IPC分类号： G06F9/45
CPC分类号： G06F8/45 , G06F8/451 , G06F8/456
摘要： Partitioning programs between a general purpose core and one or more accelerators is provided. A compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.
摘要翻译：提供通用核心和一个或多个加速器之间的分区程序。提供了一种编译器前端，用于将相应高级编程语言中的程序源代码转换为中间代码表示。该中间代码表示被提供给过程间优化器，其确定程序的每个部分应执行哪个核心处理器或加速器，并且基于该组决定将程序分割成子程序。过程间优化器可以进一步向分区添加指令以根据需要协调和同步子程序。每个子程序被编译在用于执行子程序的特定核心处理器或加速器的指令集架构的适当编译器后端上。编译的子程序然后链接从而生成可执行程序。

9. 发明申请

US20140040598A1 VECTOR PROCESSING IN AN ACTIVE MEMORY DEVICE 审中-公开
标题翻译：主动存储器件中的矢量处理
公开(公告)号：US20140040598A1
公开(公告)日：2014-02-06
申请号：US13569359
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括用于有源存储器设备中的向量处理的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。确定并行重复子指令执行的迭代次数。基于迭代计数，由处理元件并行地重复子指令的执行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

10. 发明申请

US20130096902A1 Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis 有权
标题翻译：软错误率分析的硬件执行驱动应用级别降级计算
公开(公告)号：US20130096902A1
公开(公告)日：2013-04-18
申请号：US13271827
申请日：2011-10-12
申请人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
发明人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
IPC分类号： G06F17/50
CPC分类号： G01R31/31816 , G01R31/318357 , G06F17/5022
摘要： Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
摘要翻译：提供了用于预测软错误对集成电路器件设计的影响的机制。数据处理系统被配置为实现统一的降额工具，其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载，并在执行应用程序工作负载期间将故障注入到现有硬件中，以生成应用程序降级信息。机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。

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