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    • 6. 发明授权
    • Techniques for reducing thread overhead for systems with multiple multi-threaded processors
    • 用于减少具有多个多线程处理器的系统的线程开销的技术
    • US08453147B2
    • 2013-05-28
    • US11446609
    • 2006-06-05
    • Robert JeterJohn MarshallWilliam LeeTrevor Garner
    • Robert JeterJohn MarshallWilliam LeeTrevor Garner
    • G06F9/46
    • G06F9/5027
    • Techniques for processing requests from a processing thread for a shared resource shared among threads on one or more processors include receiving a bundle of requests from a portion of a thread that is executed during a single wake interval on a particular processor. The bundle includes multiple commands for one or more shared resources. The bundle is processed at the shared resource(s) to produce a bundle result. The bundle result is sent to the particular processor. The thread undergoes no more than one wake interval to sleep interval cycle while the bundle commands are processed at the shared resource(s). These techniques allow a lock for shared resource(s) to be obtained, used and released all while the particular thread is sleeping, so that locks are held for shorter times than in conventional approaches. Using these techniques, line rate packet processing is more readily achieved in routers with multiple multi-threaded processors.
    • 用于处理来自处理线程的用于在一个或多个处理器上的线程之间共享的共享资源的请求的技术包括从在特定处理器上的单个唤醒间隔期间执行的线程的一部分接收一束请求。 捆绑包包含一个或多个共享资源的多个命令。 在共享资源处理捆绑包以产生捆绑结果。 捆绑结果发送到特定的处理器。 线程经历不超过一个唤醒间隔到休眠间隔周期,而束命令在共享资源处被处理。 这些技术允许在特定线程正在休眠期间获得,使用和释放共享资源的锁定,使得锁比一般方法保持更短的时间。 使用这些技术,在具有多个多线程处理器的路由器中更容易实现线路速率分组处理。
    • 7. 发明授权
    • Apparatus for hardware-software classification of data packet flows
    • 用于数据包流的硬件分类的装置
    • US08228908B2
    • 2012-07-24
    • US11484791
    • 2006-07-11
    • Trevor GarnerWilliam LeeHanli ZhangMartin Hughes
    • Trevor GarnerWilliam LeeHanli ZhangMartin Hughes
    • H04L12/28
    • H04L45/00H04L45/302H04L45/38H04L45/60H04L47/10H04L47/2408H04L47/2441H04L47/34H04L49/90H04L49/901
    • An apparatus for routing data packets includes a network interface, a memory, a general purpose processor and a flow classifier. The memory stores a flow structure. Every packet in one flow has identical values for a set of data fields in the packet. The memory stores instruction that cause the processor to receive missing flow data and to add the missing flow to the flow structure. The apparatus forwards a packet based on the flow. The flow classifier determines a particular flow and whether it is already stored in the flow structure. If not, then the classifier determines whether that flow has already been sent to the processor as missing data. If not, then the classifier stores into a different data structure data that indicates the flow has been sent to the processor but is not yet included in the flow data structure, and sends missing data to the processor.
    • 用于路由数据分组的装置包括网络接口,存储器,通用处理器和流分类器。 存储器存储流程结构。 一个流中的每个数据包对于数据包中的一组数据字段具有相同的值。 存储器存储使得处理器接收丢失的流数据并将丢失的流添加到流结构的指令。 该装置基于流转发分组。 流分类器确定特定的流程以及它是否已经存储在流结构中。 如果没有,则分类器确定该流是否已经作为丢失数据发送到处理器。 如果不是,则分类器将不同的数据结构存储在指示流已经发送到处理器但尚未包括在流数据结构中的数据中,并将丢失的数据发送到处理器。
    • 8. 发明申请
    • SYSTEMS AND METHODS FOR PROVIDING EXTENSIBLE ELECTRONIC LEARNING SYSTEMS
    • 提供可扩展电子学习系统的系统和方法
    • US20110167026A1
    • 2011-07-07
    • US12958263
    • 2010-12-01
    • John Allan BakerJeremy Jason AugerWilliam Lee
    • John Allan BakerJeremy Jason AugerWilliam Lee
    • G06F15/18
    • G09B19/18
    • An extensible electronic learning system having at least one learning management system having a learning management processor and a learning management memory operatively coupled thereto, said processor programmed for executing at least one learning management service and providing at least one extensible integration module. Each extensible integration module includes a predefined vendor services interface comprising at least one vendor services definition, and a vendor configuration upload component for receiving vendor configuration settings about at least one vendor. The at least one vendor having a vendor processor and a vendor memory operatively coupled thereto, said vendor processor programmed for executing a least one vendor services, the at least one of said vendor services implementing the at least one of said vendor service definition, and providing at least one vendor integration module, each vendor integration module comprising the predefined vendor services interface and the vendor configuration settings. The vendor configuration settings are received by the extensible integration module such that the learning management system may request the at least one of said vendor services based on the extensible integration module.
    • 一种具有至少一个学习管理系统的可扩展电子学习系统,该学习管理系统具有可操作地耦合到其上的学习管理处理器和学习管理存储器,所述处理器被编程为执行至少一个学习管理服务并提供至少一个可扩展集成模块。 每个可扩展集成模块包括包括至少一个供应商服务定义的预定义供应商服务接口和用于接收关于至少一个供应商的供应商配置设置的供应商配置上载组件。 所述至少一个供应商具有供应商处理器和与其可操作地耦合的供应商存储器,所述供应商处理器被编程为执行至少一个供应商服务,所述供应商服务中的至少一个实现所述供应商服务定义中的至少一个,并且提供 至少一个供应商集成模块,每个供应商集成模块包括预定义的供应商服务接口和供应商配置设置。 供应商配置设置由可扩展集成模块接收,使得学习管理系统可以基于可扩展集成模块来请求所述供应商服务中的至少一个。
    • 9. 发明申请
    • NETWORK PROTOCOL HEADER ALIGNMENT
    • 网络协议头对齐
    • US20110064081A1
    • 2011-03-17
    • US12947535
    • 2010-11-16
    • William LeeMichael WrightJoydeep ChowdhurySriram HaridasMartin Hughes
    • William LeeMichael WrightJoydeep ChowdhurySriram HaridasMartin Hughes
    • H04L12/56
    • H04L45/60H04L45/00H04L49/602
    • Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.
    • 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中,确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存,用于确定类型。 此外,基于分类,处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题,从而节省高速缓存的多余的加载和弹出。
    • 10. 发明申请
    • Glass Breaking Device
    • 玻璃破碎装置
    • US20100301088A1
    • 2010-12-02
    • US12676801
    • 2008-09-08
    • Ciaran PurdyWilliam Lee
    • Ciaran PurdyWilliam Lee
    • B26F3/00
    • A62B3/005Y10T225/371
    • A device for breaking glass, arranged to be mounted on a pane of a breakable substrate, and being actuatable to break the pane. In one embodiment, the device comprises a base, a plunger moveable relative the base and a pin extending from and axially moveable relative the plunger, wherein the plunger is moveable relative the base from a retracted to an extended position so when the base is placed against a first pane, a distal end of the pin strikes and breaks the first pane, and the pin is moveable relative the plunger from a retracted position to an extended position, with the plunger in its extended position, such that the distal end of the pin strikes and breaks a second pane parallel to the first pane. Preferably, the plunger and pin are biased to an extended position each by a biasing means.
    • 一种用于破碎玻璃的装置,布置成安装在可破坏的基板的窗格上,并且可致动以破坏玻璃板。 在一个实施例中,该装置包括基座,柱塞可相对于基座移动,并且销可相对于柱塞延伸并且可相对于柱塞轴向移动,其中柱塞可相对于基座从缩回位置移动到延伸位置,因此当基座抵靠 第一窗格,销的远端撞击并破坏第一窗格,并且销可以相对于柱塞从缩回位置移动到延伸位置,其中柱塞处于其延伸位置,使得销的远端 打开并打破平行于第一个窗格的第二个窗格。 优选地,柱塞和销被偏置装置偏置到延伸位置。