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1. 发明授权

US06518071B1 Magnetoresistive random access memory device and method of fabrication thereof 失效
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US06518071B1
公开(公告)日：2003-02-11
申请号：US10109429
申请日：2002-03-28
申请人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
发明人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
IPC分类号： H01L2100
CPC分类号： H01L43/12
摘要： A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.
摘要翻译：一种制造具有锥形的MRAM器件的方法，包括以下步骤：提供衬底，形成位于衬底上的电介质区域，对介质区域进行图案化和各向同性地蚀刻到衬底以形成沟槽，将MRAM器件沉积在沟槽，其中MRAM器件包括位于衬底上的宽度的第一铁磁区域，具有位于第一铁磁区域上的宽度的非铁磁间隔层，以及位于非铁磁间隔层上的宽度的第二铁磁区域其中所述锥形通过使所述第一铁磁性区域的宽度大于所述非铁磁间隔层的宽度而形成，并且所述非铁磁隔离层的宽度大于所述第二铁磁区域的宽度，使得所述第一铁磁性区域区域与第二铁磁区域分离。

2. 发明授权

US07105363B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 失效
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US07105363B2
公开(公告)日：2006-09-12
申请号：US11082617
申请日：2005-03-16
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

3. 发明授权

US06885074B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 有权
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US06885074B2
公开(公告)日：2005-04-26
申请号：US10306250
申请日：2002-11-27
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： G11C11/15 , H01L21/02 , H01L27/22 , H01L43/12 , H01L29/82 , H01L27/14
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

4. 发明授权

US06888743B2 MRAM architecture 有权
标题翻译： MRAM架构
公开(公告)号：US06888743B2
公开(公告)日：2005-05-03
申请号：US10331058
申请日：2002-12-27
申请人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
发明人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
IPC分类号： G11C11/15 , G11C11/02
CPC分类号： G11C11/16
摘要： An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要翻译：提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。

5. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

6. 发明授权

US07447060B2 MRAM Memory conditioning 失效
标题翻译： MRAM内存条件
公开(公告)号：US07447060B2
公开(公告)日：2008-11-04
申请号：US11678346
申请日：2007-02-23
申请人： Eric John Salter , Mark F. Deherrera , Thomas H. Lee
发明人： Eric John Salter , Mark F. Deherrera , Thomas H. Lee
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C29/00
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.
摘要翻译：根据示例性实施例，一种方法（500）包括将磁场施加到磁隧道结（MTJ）位的阵列，所述磁场的大小足以消除由MTJ中的一个所展现的中间状态位，而不会导致MTJ位中的其他位发展到中间状态。

7. 发明授权

US06956763B2 MRAM element and methods for writing the MRAM element 失效
标题翻译： MRAM元素和写入MRAM元素的方法
公开(公告)号：US06956763B2
公开(公告)日：2005-10-18
申请号：US10609288
申请日：2003-06-27
申请人： Bengt J. Akerman , Mark F. Deherrera , Bradley N. Engel , Nicholas D. Rizzo
发明人： Bengt J. Akerman , Mark F. Deherrera , Bradley N. Engel , Nicholas D. Rizzo
IPC分类号： G11C11/155 , G11C11/00
CPC分类号： G11C11/155
摘要： A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t1). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t2). The first magnetic field is adjusted to provide a third magnitude at a third time (t3) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t4) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.
摘要翻译：提供了一种用于磁电子信息设备的直接写入，其包括在第一时间（t 1> 1）处产生具有接近磁电子信息器件的第一场强的第一磁场。一旦产生具有第一幅度的第一磁场，则在第二时间（t 2> 2）处产生具有第二磁场强度的第二磁场，靠近磁电子信息装置。第一磁场被调整以在小于第一场幅度并大于零的第三时间（t 3/3）处提供第三幅度，并且调整第二磁场以提供第四磁场小于第二场强的第四时间（t> 4 ）的场强。这种直接写入与其他直接写入一起使用，并且与切换写入组合使用以写入MRAM元素而不进行初始读取。

8. 发明授权

US06545906B1 Method of writing to scalable magnetoresistance random access memory element 有权
标题翻译：写入可伸缩磁阻随机存取存储元件的方法
公开(公告)号：US06545906B1
公开(公告)日：2003-04-08
申请号：US09978859
申请日：2001-10-16
申请人： Leonid Savtchenko , Bradley N. Engel , Nicholas D. Rizzo , Mark F. Deherrera , Jason Allen Janesky
发明人： Leonid Savtchenko , Bradley N. Engel , Nicholas D. Rizzo , Mark F. Deherrera , Jason Allen Janesky
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1675
摘要： A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.
摘要翻译：一种用于切换可扩展磁阻存储单元的方法，包括以下步骤：提供夹在字线和数字线之间的磁阻存储器件，使得可以在不同时间将电流波形施加到字和数字线，以使磁场通量将器件的有效磁矩矢量旋转大约180°。磁阻存储器件包括反铁磁耦合的N个铁磁层。可以调节N以改变设备的磁性开关量。

9. 发明授权

US07158407B2 Triple pulse method for MRAM toggle bit characterization 失效
标题翻译：用于MRAM切换位特性的三脉冲方法
公开(公告)号：US07158407B2
公开(公告)日：2007-01-02
申请号：US11118145
申请日：2005-04-29
申请人： Nicholas D. Rizzo , Mark F. Deherrera , Jason A. Janesky
发明人： Nicholas D. Rizzo , Mark F. Deherrera , Jason A. Janesky
IPC分类号： G11C11/15
CPC分类号： G11C11/16 , G11C29/50
摘要： A method is provided for testing magnetic bits (3, 104, 514) of an array. A train of first (702), second (704), and third (706) pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low field and increasing in similar amounts with respect to successive trains of the first, second, and third pulses, the third pulse having a current amplitude sufficient to toggle the magnetic bit. A representative count is recorded in response to switching of the bit. The above steps are repeated and a determination is made of the current amplitude required to write and toggle the bit.
摘要翻译：提供了一种用于测试阵列的磁头（3,104,514）的方法。将第一（702），第二（704）和第三（706）脉冲串提供给期望的位，第一和第二脉冲以基本相似的低场开始，并且相对于第一，第二和第三脉冲，第三脉冲具有足以切换磁头的电流幅度。响应于位的切换记录代表计数。重复上述步骤，并确定写入和切换位所需的当前幅度。

10. 发明申请

US20080205122A1 MRAM MEMORY CONDITIONING 失效
标题翻译： MRAM内存条件
公开(公告)号：US20080205122A1
公开(公告)日：2008-08-28
申请号：US11678346
申请日：2007-02-23
申请人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
发明人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
IPC分类号： G11C11/02
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.
摘要翻译：根据示例性实施例，一种方法（500）包括将磁场施加到磁隧道结（MTJ）位的阵列，所述磁场的大小足以消除由MTJ中的一个所展现的中间状态位，而不会导致MTJ位中的其他位发展到中间状态。

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