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1. 发明申请

US20090057855A1 SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURES 审中-公开
标题翻译：半导体封装包括立体结构
公开(公告)号：US20090057855A1
公开(公告)日：2009-03-05
申请号：US11847670
申请日：2007-08-30
申请人： Maria Clemens Quinones , Erwin Victor Cruz , Marvin Gestole , Ruben P. Madrid , Connie N. Tangpuz
发明人： Maria Clemens Quinones , Erwin Victor Cruz , Marvin Gestole , Ruben P. Madrid , Connie N. Tangpuz
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49562 , H01L23/49551 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L2224/16245 , H01L2224/32245 , H01L2224/371 , H01L2224/37599 , H01L2224/40245 , H01L2224/40247 , H01L2224/73153 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die.
摘要翻译：半导体管芯封装。其包括半导体管芯，其包括第一表面和与第一表面相对的第二表面，可选的导电结构和引线框架结构。引线框架结构包括适于支撑半导体管芯的中心部分，以及耦合到引线框架结构的中心部分的多个隔离结构。支架结构可以支撑导电结构，并且导电结构附着到半导体管芯的第二表面。

2. 发明授权

US07402462B2 Folded frame carrier for MOSFET BGA 有权
标题翻译： MOSFET BGA的折叠框架载体
公开(公告)号：US07402462B2
公开(公告)日：2008-07-22
申请号：US11179348
申请日：2005-07-12
申请人： Ruben P. Madrid , Marvin Gestole , Erwin Victor R. Cruz , Romel N. Madatad , Arniel Jaud , Paul Armand Calo
发明人： Ruben P. Madrid , Marvin Gestole , Erwin Victor R. Cruz , Romel N. Madatad , Arniel Jaud , Paul Armand Calo
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/495
CPC分类号： H01L23/49562 , H01L21/4842 , H01L23/49503 , H01L2224/16 , H01L2924/01322 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
摘要翻译：折叠框架托架具有管芯附接垫（DAP）30和一个或多个折叠边32,33,34,35。每个折叠边缘具有一个或多个螺栓36，并且每个螺柱具有梯形末端。折叠框架托架可以由单规格铜或铜合金制成。可以在引线框架的相对的导轨之间形成多个折叠的框架架。折叠的边缘用一个释放槽切割。尖端形成在DAP的边缘，然后将尖端竖立折叠。尖端提供与安装在DAP上的功率半导体的后表面上的端子的电连接。

3. 发明授权

US07002240B2 Semiconductor leadframe for staggered board attach 有权
标题翻译：用于交错板的半导体引线框连接
公开(公告)号：US07002240B2
公开(公告)日：2006-02-21
申请号：US10779117
申请日：2004-02-12
申请人： Ruben P. Madrid
发明人： Ruben P. Madrid
IPC分类号： H01L23/495
CPC分类号： H01L23/49555 , H01L21/4842 , H01L2924/0002 , Y10T29/49121 , H01L2924/00
摘要： The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.
摘要翻译：该半导体集成电路器件包括一个平面引线框，其具有以交替顺序排列成第一和第二多个的引线段，所述段具有靠近芯片安装焊盘的其内部尖端以及远离安装焊盘的外部尖端。外部尖端具有可焊接表面。所有外部尖端从引线框架平面向远离外部基板上的预期附接位置的方向弯曲，使得第一段多个与平面形成约70±1°的角度，并且第二段多个形成约 75±1°（见图4）。因此，外部尖端产生适合于焊接附着到外部基板的交错引线图案。

4. 发明申请

US20110133318A1 SiP SUBSTRATE 有权
标题翻译： SiP基板
公开(公告)号：US20110133318A1
公开(公告)日：2011-06-09
申请号：US13005618
申请日：2011-01-13
申请人： Maria Clemens Y. Quinones , Ruben P. Madrid
发明人： Maria Clemens Y. Quinones , Ruben P. Madrid
IPC分类号： H01L23/495 , H01L21/98 , H01L21/60
CPC分类号： H01L23/49861 , H01L21/56 , H01L25/0655 , H01L2224/16225 , H01L2224/32225 , H01L2224/48465 , H01L2224/73265 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.
摘要翻译：在本说明书中公开了一种包括系统的封装基板，其包括用于允许对集成电路进行精细倾斜连接的互连基板。互连基板在其上表面上包括用于接收集成电路的中心区域。互连基板还具有将上表面上的精细倾斜的触点电连接到下表面上的较大倾斜触点的互连。较大的倾斜触点连接到导电迹线框架。所得到的组件与多个其它被配置为通过导电迹线彼此相互作用的其它装置一起封装在模制化合物中。

5. 发明申请

US20090057852A1 THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：热增强半导体封装
公开(公告)号：US20090057852A1
公开(公告)日：2009-03-05
申请号：US11845560
申请日：2007-08-27
申请人： Ruben P. Madrid
发明人： Ruben P. Madrid
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L24/33 , H01L23/4334 , H01L23/49524 , H01L23/49562 , H01L23/544 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L2223/54433 , H01L2223/54473 , H01L2224/1134 , H01L2224/13111 , H01L2224/13147 , H01L2224/16245 , H01L2224/2919 , H01L2224/32245 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/3754 , H01L2224/73253 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/18301 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.
摘要翻译：公开了一种半导体管芯封装。半导体管芯封装包括半导体管芯，其包括在第一顶部半导体管芯表面处的输入端和在第二下部半导体管芯表面处的输出端。具有第一引线框架表面和与第一引线框架表面相对的第二引线框架表面的引线框架在半导体管芯封装中并且耦合到第一顶部半导体管芯表面。具有第一夹子表面和第二夹子表面的夹子联接到第二底部半导体管芯表面。具有外部成型材料表面的成型材料覆盖引线框，夹子和半导体管芯的至少一部分。第一引线框架表面和第一夹子表面被模制材料暴露，并且第一引线框架表面，第一夹子表面和模制材料的外部模制材料表面形成半导体管芯封装的外表面。

6. 发明授权

US08193622B2 Thermally enhanced thin semiconductor package 有权
标题翻译：热增强薄型半导体封装
公开(公告)号：US08193622B2
公开(公告)日：2012-06-05
申请号：US12717012
申请日：2010-03-03
申请人： Ruben P. Madrid
发明人： Ruben P. Madrid
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L24/33 , H01L23/4334 , H01L23/49524 , H01L23/49562 , H01L23/544 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L2223/54433 , H01L2223/54473 , H01L2224/1134 , H01L2224/13111 , H01L2224/13147 , H01L2224/16245 , H01L2224/2919 , H01L2224/32245 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/3754 , H01L2224/73253 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/18301 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.
摘要翻译：公开了一种半导体管芯封装。半导体管芯封装包括半导体管芯，其包括在第一顶部半导体管芯表面处的输入端和在第二下部半导体管芯表面处的输出端。具有第一引线框架表面和与第一引线框架表面相对的第二引线框架表面的引线框架在半导体管芯封装中并且耦合到第一顶部半导体管芯表面。具有第一夹子表面和第二夹子表面的夹子联接到第二底部半导体管芯表面。具有外部成型材料表面的成型材料覆盖引线框，夹子和半导体管芯的至少一部分。第一引线框架表面和第一夹子表面被模制材料暴露，并且第一引线框架表面，第一夹子表面和模制材料的外部模制材料表面形成半导体管芯封装的外表面。

7. 发明授权

US08193618B2 Semiconductor die package with clip interconnection 有权
标题翻译：半导体管芯封装带夹子互连
公开(公告)号：US08193618B2
公开(公告)日：2012-06-05
申请号：US12334249
申请日：2008-12-12
申请人： Ruben P. Madrid
发明人： Ruben P. Madrid
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49562 , H01L21/561 , H01L23/3107 , H01L23/49524 , H01L24/16 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/84 , H01L24/92 , H01L24/97 , H01L2224/13099 , H01L2224/16 , H01L2224/16245 , H01L2224/32245 , H01L2224/371 , H01L2224/37147 , H01L2224/40245 , H01L2224/73253 , H01L2224/8385 , H01L2224/84385 , H01L2224/8485 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2224/81 , H01L2224/84 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure. The second surface of the semiconductor die is proximate to the clip structure, and a molding material covers at least the semiconductor die and at least a portion of the side surfaces of the protruding portion.
摘要翻译：半导体管芯封装。半导体管芯封装包括引线框结构，其包括第一引线结构，其包括管芯附接焊盘，第二引线结构和第三引线结构。它还包括包括第一表面和第二表面的半导体管芯。半导体管芯位于引线框结构的管芯连接焊盘上。第一表面靠近管芯附接垫。半导体管芯封装进一步包括夹结构，其包括第一互连结构和第二互连结构，第一互连结构包括平面部分和突出部分，突出部分包括外表面和限定外表面的侧表面。突出部分从第一互连结构的平面部分延伸。半导体管芯的第二表面靠近夹子结构，并且模制材料至少覆盖半导体管芯和突出部分的侧表面的至少一部分。

8. 发明授权

US07893548B2 SiP substrate 有权
标题翻译： SiP基板
公开(公告)号：US07893548B2
公开(公告)日：2011-02-22
申请号：US12053707
申请日：2008-03-24
申请人： Maria Clemens Y. Quinones , Ruben P. Madrid
发明人： Maria Clemens Y. Quinones , Ruben P. Madrid
IPC分类号： H01L23/28
CPC分类号： H01L23/49861 , H01L21/56 , H01L25/0655 , H01L2224/16225 , H01L2224/32225 , H01L2224/48465 , H01L2224/73265 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.
摘要翻译：在本说明书中公开了一种包括系统的封装基板，其包括用于允许对集成电路进行精细倾斜连接的互连基板。互连基板在其上表面上包括用于接收集成电路的中心区域。互连基板还具有将上表面上的精细倾斜的触点电连接到下表面上的较大倾斜触点的互连。较大的倾斜触点连接到导电迹线框架。所得到的组件与多个其它被配置为通过导电迹线彼此相互作用的其它装置一起封装在模制化合物中。

9. 发明授权

US06707135B2 Semiconductor leadframe for staggered board attach 有权
标题翻译：用于交错板的半导体引线框连接
公开(公告)号：US06707135B2
公开(公告)日：2004-03-16
申请号：US09990846
申请日：2001-11-21
申请人： Ruben P. Madrid
发明人： Ruben P. Madrid
IPC分类号： H01L23495
CPC分类号： H01L23/49555 , H01L21/4842 , H01L2924/0002 , Y10T29/49121 , H01L2924/00
摘要： The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.
摘要翻译：该半导体集成电路器件包括一个平面引线框，其具有以交替顺序排列成第一和第二多个的引线段，所述段具有靠近芯片安装焊盘的其内部尖端以及远离安装焊盘的外部尖端。外部尖端具有可焊接表面。所有外部尖端从引线框架平面向远离外部基板上的预期附接位置的方向弯曲，使得第一段多个与平面形成约70±1°的角度，并且第二段多个形成约 75±1°（见图4）。因此，外部尖端产生适合于焊接附着到外部基板的交错引线图案。

10. 发明授权

US08372690B2 SiP substrate 有权
标题翻译： SiP基板
公开(公告)号：US08372690B2
公开(公告)日：2013-02-12
申请号：US13005618
申请日：2011-01-13
申请人： Maria Clemens Y. Quinones , Ruben P. Madrid
发明人： Maria Clemens Y. Quinones , Ruben P. Madrid
IPC分类号： H01L21/00
CPC分类号： H01L23/49861 , H01L21/56 , H01L25/0655 , H01L2224/16225 , H01L2224/32225 , H01L2224/48465 , H01L2224/73265 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.
摘要翻译：在本说明书中公开了一种包括系统的封装基板，其包括用于允许对集成电路进行精细倾斜连接的互连基板。互连基板在其上表面上包括用于接收集成电路的中心区域。互连基板还具有将上表面上的精细倾斜的触点电连接到下表面上的较大倾斜触点的互连。较大的倾斜触点连接到导电迹线框架。所得到的组件与多个其它被配置为通过导电迹线彼此相互作用的其它装置一起封装在模制化合物中。

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