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1. 发明授权

US4504930A Charge-coupled device 失效
标题翻译：电荷耦合器件
公开(公告)号：US4504930A
公开(公告)日：1985-03-12
申请号：US414109
申请日：1982-09-02
申请人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
发明人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
IPC分类号： G11C27/04 , G11C19/28 , H01L21/339 , H01L27/105 , H01L29/762 , G11C13/00
CPC分类号： H01L27/1057 , G11C19/287
摘要： The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.
摘要翻译：本发明涉及一种电荷耦合SPS存储器，其包括串联输入寄存器，并联部分和串联输出寄存器。为了增加保持时间，泄漏电流漏极区域设置在存储器的旁边。由于在通过并行部分的最外面寄存器的传输期间由于泄漏电流而收集的电荷最大，所以平行部分的侧面仅由虚拟寄存器组成的排水区域进行屏蔽。图。 1。

2. 发明授权

US4599710A Integrated memory circuit of a series-parallel-series type 失效
标题翻译：串并联型集成式存储电路
公开(公告)号：US4599710A
公开(公告)日：1986-07-08
申请号：US605958
申请日：1984-05-01
申请人： Marcellinus J. M. Pelgrom , Johannes G. Raven , Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. J. C. Annegarn
发明人： Marcellinus J. M. Pelgrom , Johannes G. Raven , Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. J. C. Annegarn
IPC分类号： H04N5/907 , G11C5/06 , G11C7/00 , G11C7/22 , G11C8/18 , G11C11/401 , G11C19/28
CPC分类号： G11C19/285 , G11C5/066 , G11C7/22 , G11C8/18
摘要： In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).
摘要翻译：在需要写入时钟信号（at 19），传输时钟信号（25）和读取时钟信号（31））的串并联串行存储器电路（3）中，由于时钟信号处理提供电路（23），仅施加两个时钟信号（至33和35）。使用门电路（41），可以从一个时钟信号（施加到35）获得由脉冲持续时间变化提供的附加信息，以适应存储器电路（图1）的时间延迟。

3. 发明授权

US4766332A Detecting binary information from a charge transfer device 失效
标题翻译：从电荷转移装置检测二进制信息
公开(公告)号：US4766332A
公开(公告)日：1988-08-23
申请号：US704891
申请日：1985-02-22
申请人： Marcellinus J. M. Pelgrom , Hendrik A. Harwig , Jan W. Slotboom
发明人： Marcellinus J. M. Pelgrom , Hendrik A. Harwig , Jan W. Slotboom
IPC分类号： G11C27/04 , G11C19/28 , H01L29/78 , H03K5/24
CPC分类号： G11C19/285
摘要： A method of detecting binary information from the pulse-shaped output signal of a CCD uses a varying reference voltage which depends on the amplitude of the last pulse detected, in order to render the detection system immune to pulse distortion as a result of transfer losses in the CCD.
摘要翻译：从CCD的脉冲输出信号检测二进制信息的方法使用取决于检测到的最后脉冲的振幅的变化的参考电压，以使检测系统免受作为传输损失的脉冲失真 CCD。

4. 发明授权

US4627083A Charge transfer device output 失效
标题翻译：电荷转移装置输出
公开(公告)号：US4627083A
公开(公告)日：1986-12-02
申请号：US841907
申请日：1986-03-20
申请人： Marcellinus J. M. Pelgrom , Jan W. Slotboom
发明人： Marcellinus J. M. Pelgrom , Jan W. Slotboom
IPC分类号： G11C19/28 , G11C27/04 , H01L21/339 , H01L27/148 , H01L29/76 , H01L29/762 , H01L29/772 , H04N5/335 , H01L29/78
CPC分类号： G11C19/285 , G11C27/04
摘要： The invention relates to a charge-coupled device, in which the reset transistor of the output is clocked--with a positive threshold voltage--by a maximum voltage equal to the supply voltage V.sub.DD. The drain (14) of the reset transistor is adjusted by means of an auxiliary transistor (T.sub.1) controlled by a current source (T.sub.2) and having the same threshold voltage, whose gate (21) is applied to V.sub.DD and whose source (22) is connected to the drain (14) of the reset transistor. Due to the fact that the maximum gate voltage is equal to V.sub.DD, additional voltage sources, such as charge pumps, for generating voltages higher than V.sub.DD are superfluous.
摘要翻译：本发明涉及一种电荷耦合器件，其中输出的复位晶体管以正的阈值电压被施加等于电源电压VDD的最大电压。复位晶体管的漏极（14）借助由电流源（T2）控制的辅助晶体管（T1）进行调节，并具有相同的阈值电压，其栅极（21）施加于VDD，源极（22）连接到复位晶体管的漏极（14）。由于最大栅极电压等于VDD的事实，用于产生高于VDD的电压的附加电压源（例如电荷泵）是多余的。

5. 发明授权

US4563752A Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized 失效
标题翻译：包括冗余并联存储寄存器的串/并行/串行移位寄存器存储器，以及包括如此组织的图像存储器的显示装置
公开(公告)号：US4563752A
公开(公告)日：1986-01-07
申请号：US501464
申请日：1983-06-06
申请人： Marcellinus J. M. Pelgrom , Arie Slob , Hendrik A. Harwig , Jan W. Slotboom
发明人： Marcellinus J. M. Pelgrom , Arie Slob , Hendrik A. Harwig , Jan W. Slotboom
IPC分类号： G11C11/14 , G06F11/10 , G09G5/00 , G09G5/36 , G11C19/00 , G11C27/04 , H01L21/339 , H01L29/762 , G11C19/08 , G06F11/20
CPC分类号： G06F11/1008 , G06F11/1076
摘要： A series/parallel/series shift register memory comprises a substrate on which there are provided storage positions for multivalent data elements. There is provided a redundancy generator for generating one or more redundant code elements on the basis of a group of data elements, said redundant code elements being applied to the series input of the shift register memory later than the associated data elements. The code elements are conducted through parallel-connected storage registers which are shorter than those used for the associated data elements, so that a redundancy reducer receives the redundant code elements from a series output before the associated data elements appear on this series output. The reduction of the storage registers, expressed in periods of the shift drive, can be performed in different ways from a technological point of view.
摘要翻译：串联/并联/串联移位寄存器存储器包括其上存在用于多值数据元素的存储位置的衬底。提供了一种冗余生成器，用于基于一组数据元素生成一个或多个冗余代码元素，所述冗余代码元素比相关联的数据元素晚于所述移位寄存器存储器的串行输入。代码元素通过并行连接的存储寄存器进行传输，这些存储寄存器比用于相关联的数据元件的存储寄存器更短，从而冗余减少器在相关的数据元素出现在该串行输出之前从串行输出接收冗余代码元素。从技术的角度来看，可以以不同的方式执行在变速驱动器的周期中表示的存储寄存器的减少。

6. 发明授权

US4669100A Charge-coupled device having a buffer electrode 失效
标题翻译：具有缓冲电极的电荷耦合器件
公开(公告)号：US4669100A
公开(公告)日：1987-05-26
申请号：US910795
申请日：1986-09-22
申请人： Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. M. Pelgrom
发明人： Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. M. Pelgrom
IPC分类号： H01L21/339 , G11C19/28 , H01L27/105 , H01L27/148 , H01L29/762 , H04M1/82 , G11C11/34 , H01L29/78
CPC分类号： H01L27/1057 , G11C19/287 , H04M1/82
摘要： A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations of the de-interlacing electrodes, and associated complex clock control, a narrow extra electrode (41) is provided between the de-interlacing electrodes and the series-output register (B). This electrode (41) may serve as a buffer electrode for each half row of information (from 1a or 1b) while the preceding half row (from 1b or 1a) is transported through the series output register.
摘要翻译：串联并行串行存储器或其他并行到系列CCD的电荷信号在交替的并行通道1a和1b中隔行扫描，并且在平行到串联的转换处的去隔行电极（19,20,21,22）。为了避免由于去隔行电极的梳状电极配置和相关的复合时钟控制引起的延迟效应，在去隔行电极和串联输出寄存器之间提供了窄的额外电极（41） B）。该电极（41）可以用作每半行信息的缓冲电极（从1a或1b），而前半行（1b或1a）通过串联输出寄存器传输。

7. 发明授权

US4627082A Semiconductor device for obtaining an accurate threshold voltage adjustment 失效
标题翻译：用于获得准确的阈值电压调节的半导体器件
公开(公告)号：US4627082A
公开(公告)日：1986-12-02
申请号：US634923
申请日：1984-07-26
申请人： Marcellinus J. M. Pelgrom , Hendrik A. Harwig , Jan W. Slotboom
发明人： Marcellinus J. M. Pelgrom , Hendrik A. Harwig , Jan W. Slotboom
IPC分类号： H01L29/762 , G05F3/24 , H01L21/339 , H01L27/088 , H01L29/10 , H01L29/76 , H01L29/768 , H01L29/772 , G11C19/28 , H01L29/78
CPC分类号： H01L29/1033 , G05F3/242 , H01L27/088 , H01L29/76808
摘要： The invention relates to an integrated MOS circuit comprising a MOS transistor which is connected as a resistor and which, when conducting current, generates a voltage which is supplied to the source/gate of a second field effect device. In order to obtain a suitable current adjustment, the two channel widths are chosen so that due to narrow channel effects, a difference (though small) in threshold voltage is obtained. The invention is of particular interest for CCD input circuits for generating a small offset voltage required for supplying FAT-zero.
摘要翻译：本发明涉及一种集成MOS电路，其包括作为电阻器连接的MOS晶体管，并且在导通电流时产生提供给第二场效应器件的源极/栅极的电压。为了获得适当的电流调节，选择两个通道宽度，使得由于窄的通道效应，获得阈值电压的差值（尽管小）。本发明对于用于产生提供FAT-zero所需的小偏移电压的CCD输入电路是特别有意义的。

8. 发明授权

US5081372A Sample-and-hold device 失效
标题翻译：样品保持装置
公开(公告)号：US5081372A
公开(公告)日：1992-01-14
申请号：US528658
申请日：1990-05-24
申请人： Marcellinus J. M. Pelgrom
发明人： Marcellinus J. M. Pelgrom
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： A sample-and-hold device provided with a series arrangement of a first and a second integrating circuit, each including an input, an output and a control signal input. The output of the first integrating circuit is coupled to the input of the second integrating circuit. A control unit supplies a first and a second control signal to the control signal inputs of the first and the second integrating circuit, respectively. The output of the second integrating circuit is fed back to the input of the first integrating circuit. The first integrating circuit is controlled by the first control signal in a manner such that in the first integrating circuit an integration step is performed upon the difference between the input voltage on the input of the first integrating circuit and the output voltage fed back from the output of the second integrating circuit. The second integrating circuit is controlled by the second control signal in a manner such that upon completion of the integration step in the first integrating circuit, an integration step is performed upon the output signal of the first integrating circuit.This arrangement provides comparatively small signal variations at the inputs of the amplifier stages in the integrating circuits and thus reduces signal distortion.

9. 发明授权

US5079552A Digital-to-analog converter 失效
标题翻译：数字到模拟转换器
公开(公告)号：US5079552A
公开(公告)日：1992-01-07
申请号：US624386
申请日：1990-12-04
申请人： Marcellinus J. M. Pelgrom , Martien van der Veen
发明人： Marcellinus J. M. Pelgrom , Martien van der Veen
IPC分类号： H03M1/08 , H03M1/06 , H03M1/74 , H03M1/76
CPC分类号： H03M1/0602 , H03M1/765
摘要： Digital-to-analog converter having a reference voltage divider and a selection circuit by which the voltage at one of the nodal points of the reference voltage divider can be switched-through to the output of the converter. The selection circuit is controlled by selection signals coming from a decoder circuit by which the digital input signal is decoded. In addition, the converter includes a bias voltage divider which can apply different bias voltages to a level shifting circuit by which the signal level of the selection signals can be shifted.

10. 发明授权

US6100686A Magnetic field sensor with double wheatstone bridge having magneto-resistive elements 失效
标题翻译：具有双重惠斯通电桥的磁场传感器具有磁阻元件
公开(公告)号：US6100686A
公开(公告)日：2000-08-08
申请号：US96074
申请日：1998-06-11
申请人： Martinus H. W. M. Van Delden , Kars-Michiel H. Lenssen , Marcellinus J. M. Pelgrom , Gerjan F. A. Van De Walle
发明人： Martinus H. W. M. Van Delden , Kars-Michiel H. Lenssen , Marcellinus J. M. Pelgrom , Gerjan F. A. Van De Walle
IPC分类号： G01R33/09 , G11B5/39 , H01L43/08 , H01L43/02
CPC分类号： B82Y25/00 , B82Y10/00 , G01R33/09 , G01R33/096 , G11B2005/3996 , G11B5/3945
摘要： A magnetic field sensor has a substrate on which a plurality of resistive elements form a double Wheatstone bridge circuit, at least one of the resistive elements in each bridge having a magneto-resistive characteristic. The two bridges are identical except in that, if a given magneto-resistive element in a given branch in one bridge has a positive output polarity, then the corresponding magneto-resistive element in the same branch in the other bridge will have a negative output polarity. By adding the output signals of the two Wheatstone bridges a zero-point offset of the sensor can be determined and eliminated. There is no need to employ the so-called flipping technique employed for that purpose in conventional sensors, which requires increased power consumption.
摘要翻译：磁场传感器具有多个电阻元件形成双惠斯登电桥电路的基板，每个桥中的至少一个电阻元件具有磁阻特性。这两个桥是相同的，除了在一个桥中的给定分支中的给定磁阻元件具有正输出极性的情况下，另一个桥中相同分支中的对应的磁阻元件将具有负的输出极性。通过添加两个惠斯登电桥的输出信号，可以确定和消除传感器的零点偏移。在传统传感器中，不需要采用所谓的翻转技术，这就需要增加功耗。

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