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1. 发明授权

US5079552A Digital-to-analog converter 失效
标题翻译：数字到模拟转换器
公开(公告)号：US5079552A
公开(公告)日：1992-01-07
申请号：US624386
申请日：1990-12-04
申请人： Marcellinus J. M. Pelgrom , Martien van der Veen
发明人： Marcellinus J. M. Pelgrom , Martien van der Veen
IPC分类号： H03M1/08 , H03M1/06 , H03M1/74 , H03M1/76
CPC分类号： H03M1/0602 , H03M1/765
摘要： Digital-to-analog converter having a reference voltage divider and a selection circuit by which the voltage at one of the nodal points of the reference voltage divider can be switched-through to the output of the converter. The selection circuit is controlled by selection signals coming from a decoder circuit by which the digital input signal is decoded. In addition, the converter includes a bias voltage divider which can apply different bias voltages to a level shifting circuit by which the signal level of the selection signals can be shifted.

2. 发明授权

US5081372A Sample-and-hold device 失效
标题翻译：样品保持装置
公开(公告)号：US5081372A
公开(公告)日：1992-01-14
申请号：US528658
申请日：1990-05-24
申请人： Marcellinus J. M. Pelgrom
发明人： Marcellinus J. M. Pelgrom
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： A sample-and-hold device provided with a series arrangement of a first and a second integrating circuit, each including an input, an output and a control signal input. The output of the first integrating circuit is coupled to the input of the second integrating circuit. A control unit supplies a first and a second control signal to the control signal inputs of the first and the second integrating circuit, respectively. The output of the second integrating circuit is fed back to the input of the first integrating circuit. The first integrating circuit is controlled by the first control signal in a manner such that in the first integrating circuit an integration step is performed upon the difference between the input voltage on the input of the first integrating circuit and the output voltage fed back from the output of the second integrating circuit. The second integrating circuit is controlled by the second control signal in a manner such that upon completion of the integration step in the first integrating circuit, an integration step is performed upon the output signal of the first integrating circuit.This arrangement provides comparatively small signal variations at the inputs of the amplifier stages in the integrating circuits and thus reduces signal distortion.

3. 发明授权

US4504930A Charge-coupled device 失效
标题翻译：电荷耦合器件
公开(公告)号：US4504930A
公开(公告)日：1985-03-12
申请号：US414109
申请日：1982-09-02
申请人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
发明人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
IPC分类号： G11C27/04 , G11C19/28 , H01L21/339 , H01L27/105 , H01L29/762 , G11C13/00
CPC分类号： H01L27/1057 , G11C19/287
摘要： The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.
摘要翻译：本发明涉及一种电荷耦合SPS存储器，其包括串联输入寄存器，并联部分和串联输出寄存器。为了增加保持时间，泄漏电流漏极区域设置在存储器的旁边。由于在通过并行部分的最外面寄存器的传输期间由于泄漏电流而收集的电荷最大，所以平行部分的侧面仅由虚拟寄存器组成的排水区域进行屏蔽。图。 1。

4. 发明授权

US6100686A Magnetic field sensor with double wheatstone bridge having magneto-resistive elements 失效
标题翻译：具有双重惠斯通电桥的磁场传感器具有磁阻元件
公开(公告)号：US6100686A
公开(公告)日：2000-08-08
申请号：US96074
申请日：1998-06-11
申请人： Martinus H. W. M. Van Delden , Kars-Michiel H. Lenssen , Marcellinus J. M. Pelgrom , Gerjan F. A. Van De Walle
发明人： Martinus H. W. M. Van Delden , Kars-Michiel H. Lenssen , Marcellinus J. M. Pelgrom , Gerjan F. A. Van De Walle
IPC分类号： G01R33/09 , G11B5/39 , H01L43/08 , H01L43/02
CPC分类号： B82Y25/00 , B82Y10/00 , G01R33/09 , G01R33/096 , G11B2005/3996 , G11B5/3945
摘要： A magnetic field sensor has a substrate on which a plurality of resistive elements form a double Wheatstone bridge circuit, at least one of the resistive elements in each bridge having a magneto-resistive characteristic. The two bridges are identical except in that, if a given magneto-resistive element in a given branch in one bridge has a positive output polarity, then the corresponding magneto-resistive element in the same branch in the other bridge will have a negative output polarity. By adding the output signals of the two Wheatstone bridges a zero-point offset of the sensor can be determined and eliminated. There is no need to employ the so-called flipping technique employed for that purpose in conventional sensors, which requires increased power consumption.
摘要翻译：磁场传感器具有多个电阻元件形成双惠斯登电桥电路的基板，每个桥中的至少一个电阻元件具有磁阻特性。这两个桥是相同的，除了在一个桥中的给定分支中的给定磁阻元件具有正输出极性的情况下，另一个桥中相同分支中的对应的磁阻元件将具有负的输出极性。通过添加两个惠斯登电桥的输出信号，可以确定和消除传感器的零点偏移。在传统传感器中，不需要采用所谓的翻转技术，这就需要增加功耗。

5. 发明授权

US5353027A Multistep analog-to-digital converter with error correction 失效
标题翻译：具有纠错功能的多步模数转换器
公开(公告)号：US5353027A
公开(公告)日：1994-10-04
申请号：US966208
申请日：1992-10-26
申请人： Pieter P. M. Vorenkamp , Johannes Verdaasdonk , Marcellinus J. M. Pelgrom
发明人： Pieter P. M. Vorenkamp , Johannes Verdaasdonk , Marcellinus J. M. Pelgrom
IPC分类号： H03M1/14 , H03M1/06
CPC分类号： H03M1/069 , H03M1/145
摘要： A sub-ranging analog-to-digital converter includes, in cascade, a coarse converter, a digital-to-analog converter, a subtracter circuit and a fine converter. Errors of the coarse converter are detected in the fine converter by means of an overflow detector and an underflow detector which generate an overflow signal (OF) and an underflow signal (UF), respectively. The digital output (D.sub.A) of the coarse converter is corrected by first subtracting one LBS in a decoder and then, in response to the overflow and underflow signal, adding thereto zero, one or two LBSs.
摘要翻译：子范围模数转换器级联地包括粗转换器，数模转换器，减法器电路和精细转换器。通过溢出检测器和下溢检测器分别在精细转换器中检测出粗转换器的错误，该溢出检测器和下溢检测器产生溢出信号（OF）和下溢信号（UF）。通过首先在解码器中减去一个LBS，然后响应于溢出和下溢信号，将其加到零，一个或两个LBS来校正粗变换器的数字输出（DA）。

6. 发明授权

US4872011A Plural stage switched capacitor integrating digital-to-analog converter 失效
标题翻译：集成数模转换器的多级开关电容器
公开(公告)号：US4872011A
公开(公告)日：1989-10-03
申请号：US178051
申请日：1988-04-05
申请人： Marcellinus J. M. Pelgrom , Adrianus C. J. Duinmaijer
发明人： Marcellinus J. M. Pelgrom , Adrianus C. J. Duinmaijer
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/0697 , H03M1/0607 , H03M1/682 , H03M1/806
摘要： A digital-to-analog converter for converting a digital signal having a word length n into an analog signal. The converter includes at least two switched capacitor integrators (1, 2) arranged in series and a control unit (18) for applying control signals to the integrators which perform an integration step under the influence of the control signal. Each integrator is provided with a capacitor network (11, 12) having at least two capacitors (27.1, 27.2, . . . ; 28.1, 28.2, . . . ) coupled between the input (13; 4) of the integrator and the inverting input (-) of an associated amplifier stage (5; 6). A capacitor (9; 10) is coupled between the inverting input (-) and the output (7; 8) of this amplifier stage. The control unit is adapted to apply, in this order, a first control signal to the first integrator (1), a second control signal to the second integrator (2), a third control signal to the first integrator and a fourth control signal to the second integrator. The first integrator couples a total capacitance of M1.Cref1 and M3.Cref1 during a given time interval to the inverting input of the amplifier stage (5) under the influence of the first and the third control signal, respectively. The second integrator (2) couples a total capacitance of M2.Cref2 and M4.Cref2 during a given time interval to the inverting output of the amplifier stage (6) under the influence of the second and the fourth control signal, respectively. For converting an arbitrary n-bit digital signal, M2+M4 is equal to a constant (k) which is preferably equal to 2.sup.p in which p.ltoreq.n an offset voltage which is independent of the value of the digital signal to be converted is produced at the output (8) of the converter.

7. 发明授权

US4771445A Charge-coupled device having an improved input stage 失效
标题翻译：电荷耦合器件具有改进的输入级
公开(公告)号：US4771445A
公开(公告)日：1988-09-13
申请号：US33141
申请日：1987-03-31
申请人： Marcellinus J. M. Pelgrom , Hendrik Heijns
发明人： Marcellinus J. M. Pelgrom , Hendrik Heijns
IPC分类号： H01L29/762 , G11C19/28 , G11C27/04 , H01L21/339 , H01L29/78
CPC分类号： G11C19/285 , G11C27/04
摘要： The invention relates to a CCD having a so-called diode cut-off input, in which the input diode is applied to a reference voltage and the input signal is supplied to the input gate located in front of the first clock electrode. More particularly, if the electrodes are composed of a transfer part and a storage part with an incorporated potential difference, it is possible that, when charge is transported from the input gate to the first clock electrode, a large amount of charge is left behind. In order to avoid this and/or to be able to enlarge the dynamic range of the input signal, a MOST switch controlled by the same clock voltage as the first clock electrode is arranged between the input gate and a reference voltage, for example ground. This switch becomes conducting when the charge is transferred, as a result of which the potential level below the input gate can be adjusted above the surface potential below the transfer part of the first clock electrode.

8. 发明授权

US4599710A Integrated memory circuit of a series-parallel-series type 失效
标题翻译：串并联型集成式存储电路
公开(公告)号：US4599710A
公开(公告)日：1986-07-08
申请号：US605958
申请日：1984-05-01
申请人： Marcellinus J. M. Pelgrom , Johannes G. Raven , Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. J. C. Annegarn
发明人： Marcellinus J. M. Pelgrom , Johannes G. Raven , Jan W. Slotboom , Hendrik A. Harwig , Marcellinus J. J. C. Annegarn
IPC分类号： H04N5/907 , G11C5/06 , G11C7/00 , G11C7/22 , G11C8/18 , G11C11/401 , G11C19/28
CPC分类号： G11C19/285 , G11C5/066 , G11C7/22 , G11C8/18
摘要： In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).
摘要翻译：在需要写入时钟信号（at 19），传输时钟信号（25）和读取时钟信号（31））的串并联串行存储器电路（3）中，由于时钟信号处理提供电路（23），仅施加两个时钟信号（至33和35）。使用门电路（41），可以从一个时钟信号（施加到35）获得由脉冲持续时间变化提供的附加信息，以适应存储器电路（图1）的时间延迟。

9. 发明授权

US4987580A Charge transfer device having capacitive feedback 失效
标题翻译：具有电容反馈的电荷转移装置
公开(公告)号：US4987580A
公开(公告)日：1991-01-22
申请号：US209444
申请日：1988-06-20
申请人： Marcellinus J. M. Pelgrom , Antonius J. G. Jochijms , Arthur H. M. Van Roermund
发明人： Marcellinus J. M. Pelgrom , Antonius J. G. Jochijms , Arthur H. M. Van Roermund
IPC分类号： H01L29/762 , G11C19/28 , H01L21/339 , H01L29/768
CPC分类号： H01L29/76816 , G11C19/285
摘要： The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ). Thus, this voltage variation is an accurate measure of the supplied charge.

10. 发明授权

US4799109A Charge coupled sensor arrangement 失效
标题翻译：电荷耦合传感器布置
公开(公告)号：US4799109A
公开(公告)日：1989-01-17
申请号：US149981
申请日：1988-01-27
申请人： Leonard J. M. Esser , Marcellinus J. M. Pelgrom
发明人： Leonard J. M. Esser , Marcellinus J. M. Pelgrom
IPC分类号： H01L27/148 , H04N5/32 , H04N5/376 , H04N3/14
CPC分类号： H04N3/1525 , H01L27/14831
摘要： The invention relates to a charge-coupled image sensor of the line transfer type comprising a number of parallel lines (2-6) which are each constituted by an n-phase CCD. An electrode (12-16) of each CCD is arranged parallel to this CCD separately for each CCD. The other (n-1) electrodes (17-20) extend transversely to the charge transport direction over all CCD's. The first-mentioned electrode (12-16) is used as a selection gate and is moreover used, depending upon the applied voltage, as an integration gate or as a blocking gate during the integration period.
摘要翻译：本发明涉及一种线路传输类型的电荷耦合图像传感器，包括多个由n相CCD构成的平行线（2-6）。每个CCD的电极（12-16）分别平行于每个CCD的CCD。其他（n-1）个电极（17-20）横跨所有CCD的电荷输送方向延伸。首先提到的电极（12-16）用作选择栅极，并且根据所施加的电压，在积分期间作为积分栅极或阻挡栅极使用。

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