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    • 1. 发明申请
    • CLOSED-LOOP MULTIPHASE SLEW RATE CONTROLLER
    • 闭环多相速率控制器
    • US20130055006A1
    • 2013-02-28
    • US13219816
    • 2011-08-29
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • G06F1/04
    • G06F1/04
    • A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
    • 一种用于计算系统的转换速率控制器包括转换速率控制模块,所述转换速率控制模块还包括多个采样模块,每个采样模块对应于多个相位信号输入中的一个,其中每个采样模块接收输入信号 参考电压和采样模块各自的相位信号输入,并且其中每个采样模块在由采样模块的各个相位信号输入指示的时间段期间产生输入信号和参考电压之间的关系的相应采样; 以及有限状态机,被配置为基于来自所述采样模块的所述多个采样来输出转换速率控制信号以控制所述输入信号的转换速率。
    • 2. 发明授权
    • Closed-loop multiphase slew rate controller for signal drive in a computer system
    • 用于计算机系统中信号驱动的闭环多相转换速率控制器
    • US09009520B2
    • 2015-04-14
    • US13219816
    • 2011-08-29
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • G06F1/04G06F1/24G06F11/00
    • G06F1/04
    • A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
    • 一种用于计算系统的转换速率控制器包括转换速率控制模块,所述转换速率控制模块还包括多个采样模块,每个采样模块对应于多个相位信号输入中的一个,其中每个采样模块接收输入信号 参考电压和采样模块各自的相位信号输入,并且其中每个采样模块在由采样模块的各个相位信号输入指示的时间段期间产生输入信号和参考电压之间的关系的相应采样; 以及有限状态机,被配置为基于来自所述采样模块的所述多个采样来输出转换速率控制信号以控制所述输入信号的转换速率。
    • 6. 发明申请
    • EQUALIZED RISE AND FALL SLEW RATES FOR A BUFFER
    • 均衡的上升和缓冲器的缓冲率
    • US20140035643A1
    • 2014-02-06
    • US13567214
    • 2012-08-06
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • H03K5/12
    • H03K19/00361
    • Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.
    • 本发明的方面提供了用于平衡缓冲器的输出端的上升和下降转换速率。 在一个实施例中,一种方法包括:同时测量缓冲器输入端的上升和下降转换速率以及缓冲器输出端的上升和下降转换速率; 基于所述缓冲器的输入端的上升转换速率或所述下降转换速率中的至少一个产生转换参考; 将缓冲器输出端的上升转换速率与下降转换速率进行比较; 以及生成上升控制信号或下降控制信号中的至少一个,用于调整在缓冲器的输出处的上升转换速率或下降转换速率中的至少一个。
    • 7. 发明授权
    • Equalized rise and fall slew rates for a buffer
    • 缓冲器的平均上升和下降转换速率
    • US08638149B1
    • 2014-01-28
    • US13567214
    • 2012-08-06
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • Marcel A. KosselDaihyun LimPradeep Thiagarajan
    • H03K5/12
    • H03K19/00361
    • Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.
    • 本发明的方面提供了用于平衡缓冲器的输出端的上升和下降转换速率。 在一个实施例中,一种方法包括:同时测量缓冲器输入端的上升和下降转换速率,以及缓冲器输出端的上升和下降转换速率; 基于所述缓冲器的输入端的上升转换速率或所述下降转换速率中的至少一个产生转换参考; 将缓冲器输出端的上升转换速率与下降转换速率进行比较; 以及生成上升控制信号或下降控制信号中的至少一个,用于调整在缓冲器的输出处的上升转换速率或下降转换速率中的至少一个。