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1. 发明授权

US09135989B2 Write data preservation for non-volatile storage 有权
标题翻译：为非易失性存储写入数据保存
公开(公告)号：US09135989B2
公开(公告)日：2015-09-15
申请号：US13605583
申请日：2012-09-06
申请人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
发明人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
IPC分类号： G11C11/34 , G11C11/56
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.
摘要翻译：提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。这两组锁存器也可用于在该程序数据的编程期间存储验证状态。可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。例如，上页数据可以最初存储在一组锁存器中。当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

2. 发明授权

US08630118B2 Defective word line detection 有权
标题翻译：字线检测不良
公开(公告)号：US08630118B2
公开(公告)日：2014-01-14
申请号：US13292556
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C16/04
CPC分类号： G11C29/025 , G11C11/5628 , G11C16/0483 , G11C2029/1202 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.
摘要翻译：提供了用于检测字线中的缺陷的方法和非易失性存储系统。可能检测到“破碎”的字线缺陷。可以保持关于哪些存储元件被编程为跟踪状态的信息。然后，在完成编程之后，读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。通过跟踪哪些存储元件处于跟踪状态，可以滤除与其他状态相关联的元件，使得可以对哪些存储元件被编程不正确进行准确的评估。根据该信息，可以确定字线是否有缺陷。例如，如果存储元素太多被编程不当，则这可能表示一个破损的字线。

3. 发明申请

US20130114344A1 ERRATIC PROGRAM DETECTION FOR NON-VOLATILE STORAGE 有权
标题翻译：用于非易失性存储的ERRATIC PROGRAM检测
公开(公告)号：US20130114344A1
公开(公告)日：2013-05-09
申请号：US13292569
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3454
摘要： Methods and non-volatile storage systems are provided for determining erratically programmed storage elements, including under-programmed and over-programmed storage elements. Techniques do not require any additional data latches. A set of data latches may be used to store program data for a given memory element. This program data may be maintained after the programming is over for use in erratic program detection. In one embodiment, lockout status is kept in a data latch that is used to serially receive program data to be programmed into the storage element. Therefore, no extra data latches are required to program the storage elements and to maintain the program data afterwards.
摘要翻译：提供方法和非易失性存储系统用于确定不规则编程的存储元件，包括欠编程和过程编程的存储元件。技术不需要任何额外的数据锁存器。一组数据锁存器可用于存储给定存储器元件的程序数据。该程序数据可以在编程结束之后保持，以用于不规则的程序检测。在一个实施例中，锁定状态保存在数据锁存器中，该数据锁存器用于串行地接收要编程到存储元件中的程序数据。因此，不需要额外的数据锁存器来对存储元件进行编程并且之后维护程序数据。

4. 发明授权

US08842476B2 Erratic program detection for non-volatile storage 有权
标题翻译：用于非易失性存储的错误程序检测
公开(公告)号：US08842476B2
公开(公告)日：2014-09-23
申请号：US13292569
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/08 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3454
摘要： Methods and non-volatile storage systems are provided for determining erratically programmed storage elements, including under-programmed and over-programmed storage elements. Techniques do not require any additional data latches. A set of data latches may be used to store program data for a given memory element. This program data may be maintained after the programming is over for use in erratic program detection. In one embodiment, lockout status is kept in a data latch that is used to serially receive program data to be programmed into the storage element. Therefore, no extra data latches are required to program the storage elements and to maintain the program data afterwards.
摘要翻译：提供方法和非易失性存储系统用于确定不规则编程的存储元件，包括欠编程和过程编程的存储元件。技术不需要任何额外的数据锁存器。一组数据锁存器可用于存储给定存储器元件的程序数据。该程序数据可以在编程结束之后保持，以用于不规则的程序检测。在一个实施例中，锁定状态保存在数据锁存器中，该数据锁存器用于串行地接收要编程到存储元件中的程序数据。因此，不需要额外的数据锁存器来对存储元件进行编程并且之后维护程序数据。

5. 发明申请

US20140063961A1 WRITE DATA PRESERVATION FOR NON-VOLATILE STORAGE 有权
标题翻译：写入数据保存非易失性存储
公开(公告)号：US20140063961A1
公开(公告)日：2014-03-06
申请号：US13605583
申请日：2012-09-06
申请人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
发明人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.
摘要翻译：提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。这两组锁存器也可用于在该程序数据的编程期间存储验证状态。可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。例如，上页数据可以最初存储在一组锁存器中。当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

6. 发明申请

US20130114342A1 DEFECTIVE WORD LINE DETECTION 有权
标题翻译：有缺陷的字线检测
公开(公告)号：US20130114342A1
公开(公告)日：2013-05-09
申请号：US13292556
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C16/10 , G11C16/04 , G11C16/06
CPC分类号： G11C29/025 , G11C11/5628 , G11C16/0483 , G11C2029/1202 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.
摘要翻译：提供了用于检测字线中的缺陷的方法和非易失性存储系统。可能检测到“破碎”的字线缺陷。可以保持关于哪些存储元件被编程为跟踪状态的信息。然后，在完成编程之后，读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。通过跟踪哪些存储元件处于跟踪状态，可以滤除与其他状态相关联的元件，使得可以对哪些存储元件被编程不正确进行准确的评估。根据该信息，可以确定字线是否有缺陷。例如，如果存储元素太多被编程不当，则这可能表示一个破损的字线。

7. 发明申请

US20120166913A1 Non-Volatile Memory And Methods With Asymmetric Soft Read Points Around Hard Read Points 有权
标题翻译：非易失性存储器和方法在硬读取点周围的不对称软读点
公开(公告)号：US20120166913A1
公开(公告)日：2012-06-28
申请号：US12978348
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
IPC分类号： H03M13/05 , G06F11/10 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1072 , G11C16/26 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

8. 发明申请

US20100061151A1 MULTI-PASS PROGRAMMING FOR MEMORY WITH REDUCED DATA STORAGE REQUIREMENT 有权
标题翻译：具有减少数据存储要求的存储器的多级编程
公开(公告)号：US20100061151A1
公开(公告)日：2010-03-11
申请号：US12344763
申请日：2008-12-29
申请人： Toru Miwa , Gerrit Jan Hemink
发明人： Toru Miwa , Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3418 , G11C2211/5621
摘要： Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption.
摘要翻译：在多通道编程操作中减少非易失性存储设备中的相邻浮动栅极之间的耦合效应，同时减少程序数据存储要求。在一种方法中，存储元件被编程为不按顺序或之字形字线顺序。一个特定的字线用一个粗略的程序通道进行编程，之后用一个精细的程序通道对另一个字线进行编程，然后读取特定的字线。在另一个字线被粗略编程通道编程之前读取特定字线，其导致对特定字线的存储元件的耦合干扰。读取的数据随后用于执行特定字线的精细节目通行。这避免了同时存储多个字线的程序数据的需要，使得存储硬件可以与功耗一起减小。

9. 发明申请

US20080025099A1 Non-Volatile Memory And Control With Improved Partial Page Program Capability 有权
标题翻译：非易失性存储器和具有改进的部分页面程序能力的控制
公开(公告)号：US20080025099A1
公开(公告)日：2008-01-31
申请号：US11867598
申请日：2007-10-04
申请人： Yan Li , Yupin Fong , Toru Miwa
发明人： Yan Li , Yupin Fong , Toru Miwa
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.
摘要翻译：在非易失性存储器编程方案中，其中存储器单元被编程在两个或多个顺序编程遍中，当在第二遍期间存在不足的主机数据来编程至少一些存储器单元时，一些存储器单元可被编程到错误的阈值电压。这可以通过修改编程方案来避免这样的情况。在一个实现中，这是通过选择代码方案来实现的，该代码方案不会在第二编程遍期间将存储器单元编程到错误的阈值电压，或者通过根据不会导致单元被编程为错误状态。

10. 发明授权

US07280396B2 Non-volatile memory and control with improved partial page program capability 有权
标题翻译：非易失性存储器和具有改进的部分页面编程能力的控制
公开(公告)号：US07280396B2
公开(公告)日：2007-10-09
申请号：US11381972
申请日：2006-05-05
申请人： Yan Li , Yupin Kawing Fong , Toru Miwa
发明人： Yan Li , Yupin Kawing Fong , Toru Miwa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.
摘要翻译：在非易失性存储器编程方案中，其中存储器单元被编程在两个或多个顺序编程遍中，当在第二遍期间存在不足的主机数据来编程至少一些存储器单元时，一些存储器单元可被编程到错误的阈值电压。这可以通过修改编程方案来避免这样的情况。在一个实现中，这是通过选择代码方案来实现的，该代码方案不会在第二编程遍期间将存储器单元编程到错误的阈值电压，或者通过根据不会导致单元被编程为错误状态。

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