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    • 6. 发明授权
      US4637125A Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor 失效
    • Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
    • 制造包括双极晶体管和CMOS晶体管的半导体集成器件的方法
    • US4637125A
    • 1987-01-20
    • US847150
    • 1986-04-03
    • Hiroshi Iwasaki , Shintaro Ito
    • Hiroshi Iwasaki , Shintaro Ito
    • H01L21/8249 , H01L21/38
    • H01L21/8249
    • A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. An n.sup.+ -type buried region is selectively formed in both of these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried region, and the vertical pnp transistor is formed using the p.sup.+ -type buried region as a collector. In this case, a second p.sup.+ -type isolation diffusion region is formed to isolate an n-type base region of the vertical pnp transistor.
    • 公开了一种半导体集成器件（CBi-CMOS），其中在单个半导体衬底中形成CMOS晶体管和垂直npn和pnp晶体管，并且防止了CMOS中的闭锁现象。 还公开了制造CBi-CMOS的方法。 在CBi-CMOS中，在p型硅衬底上形成的n型外延硅层中形成四个元件，即n-MOSFET，p-MOSFET和npn和pnp垂直晶体管。 n-MOSFET形成在具有p +型掩埋区的p阱中。 在p-MOSFET的元件区域中，也形成n +型掩埋区域。 在npn和pnp垂直晶体管的元件区域中，选择性地形成第一p +型隔离扩散区域。 在npn和pnp垂直晶体管的这些元件区域中选择性地形成n +型掩埋区域。 在npn晶体管的元件区域中，使用由第一p +型隔离扩散区域包围的n型区域作为集电极形成垂直npn晶体管。 在pnp晶体管的元件区域中，在n +型掩埋区域上形成p +型掩埋区域，使用p +型掩埋区域作为集电体形成垂直pnp晶体管。 在这种情况下，形成第二p +型隔离扩散区，以隔离垂直pnp晶体管的n型基极区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US4694562A Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors 失效
    • Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors
    • 用于制造包括双极和CMOS晶体管的半导体集成器件的方法
    • US4694562A
    • 1987-09-22
    • US925266
    • 1986-10-31
    • Hiroshi Iwasaki , Shintaro Ito
    • Hiroshi Iwasaki , Shintaro Ito
    • H01L21/8249 , H01L21/38
    • H01L21/8249
    • A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. And an n.sup.+ -type buried region is selectively formed both in these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried region, and the vertical pnp transistor is formed using the p.sup.+ -type buried region as a collector. In this case, a second p.sup.+ -type isolation diffusion region is formed to isolate an n-type base region of the vertical pnp transistor.
    • 公开了一种半导体集成器件（CBi-CMOS），其中在单个半导体衬底中形成CMOS晶体管和垂直npn和pnp晶体管，并且防止了CMOS中的闭锁现象。 还公开了制造CBi-CMOS的方法。 在CBi-CMOS中，在p型硅衬底上形成的n型外延硅层中形成四个元件，即n-MOSFET，p-MOSFET和npn和pnp垂直晶体管。 n-MOSFET形成在具有p +型掩埋区的p阱中。 在p-MOSFET的元件区域中，也形成n +型掩埋区域。 在npn和pnp垂直晶体管的元件区域中，选择性地形成第一p +型隔离扩散区域。 并且在npn和pnp垂直晶体管的这些元件区域中选择性地形成n +型掩埋区域。 在npn晶体管的元件区域中，使用由第一p +型隔离扩散区域包围的n型区域作为集电极形成垂直npn晶体管。 在pnp晶体管的元件区域中，在n +型掩埋区域上形成p +型掩埋区域，使用p +型掩埋区域作为集电体形成垂直pnp晶体管。 在这种情况下，形成第二p +型隔离扩散区，以隔离垂直pnp晶体管的n型基极区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US4337115A Method of forming electrodes on the surface of a semiconductor substrate 失效
    • Method of forming electrodes on the surface of a semiconductor substrate
    • 在半导体衬底的表面上形成电极的方法
    • US4337115A
    • 1982-06-29
    • US137813
    • 1980-04-04
    • Masashi Ikeda , Shintaro Ito
    • Masashi Ikeda , Shintaro Ito
    • H01L21/306 , H01L21/027 , H01L21/28 , H01L21/768 , H01L23/485 , B05D5/12 , C23F1/02
    • H01L21/7688 , H01L21/0272 , H01L23/4855 , H01L2924/0002 , Y10S438/944 , Y10S438/951
    • There is provided a method of forming an electrode on the surface of a semiconductor substrate which comprises the steps of(A) depositing on the surface of a semiconductor substrate an insulation layer provided with at least one opening for contact between the electrode and the semiconductor substrate;(B) coating a plurality of spacer layers made of insulation material on the surface of the insulation layer inclusive of the contact opening;(C) selectively depositing a photoresist layer on the uppermost are of said plural spacer layers, said uppermost spacer layer in direct contact with the photoresist layer being designed to be etched at a lower rate than the immediately underlying spacer layer;(D) using the photoresist layers as a mask to selectively etch the spacer layers until said opening is exposed;(E) depositing a metal layer on the surface of the semiconductor substrate inclusive of said opening and photoresist layer; and(F) removing the photoresist layer and the portions of the metal layer formed, such that the portion of the metal layer which is deposited on the surface of the semiconductor substrate exposed through the opening constitute the electrode, and the spacer layers remaining on the insulation layer form protective layers for the surface of the semiconductor substrate.
    • 提供了一种在半导体衬底的表面上形成电极的方法，其包括以下步骤：（A）在半导体衬底的表面上沉积设置有至少一个用于接触电极和半导体衬底之间的开口的绝缘层 ; （B）在绝缘层的包括接触开口的表面上涂覆由绝缘材料制成的多个隔离层; （C）在所述多个间隔层的最上面选择性地沉积光致抗蚀剂层，与光致抗蚀剂层直接接触的所述最上层间隔层被设计为以比最接近的间隔层更低的速率进行蚀刻; （D）使用光致抗蚀剂层作为掩模来选择性地蚀刻间隔层，直到所述开口暴露; （E）在包括所述开口和光致抗蚀剂层的半导体衬底的表面上沉积金属层; 和（F）去除光致抗蚀剂层和形成的金属层的部分，使得沉积在通过开口暴露的半导体衬底的表面上的金属层的部分构成电极，并且间隔层保留在 绝缘层形成用于半导体衬底的表面的保护层。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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