专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5315601A Error correction method and apparatus thereof 失效
标题翻译：误差校正方法及其装置
公开(公告)号：US5315601A
公开(公告)日：1994-05-24
申请号：US707811
申请日：1991-05-30
申请人： Man-young Lee , Hak-song Park , Young-cheol Kim , Tae-yong Kim , Yong-jin Choi , Jae-moon Kim
发明人： Man-young Lee , Hak-song Park , Young-cheol Kim , Tae-yong Kim , Yong-jin Choi , Jae-moon Kim
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/15 , G06F11/10 , H03M13/151
摘要： An error correction method and apparatus for correcting multiple errors in received digital data word signals calculates syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 from a block of n received data words and a parity check matrix H. First coefficients .sigma..sub.1 and .sigma..sub.2 are calculated from the derived syndromes and a second coefficient K is calculated from the first coefficients .sigma..sub.1 and .sigma..sub.2. An error location value x.sub.1 is calculated from the second coefficient K, actual error location values X.sub.1 and X.sub.2 are calculated from the value x.sub.1, and error values Y.sub.1 and Y.sub.2 are calculated from the actual error location values X.sub.1 and X.sub.2. The received data words are then corrected by applying the calculated error values Y.sub.1 and Y.sub.2. The error location value x.sub.1 calculator is preferably constituted by logic gates which enable the apparatus to be smaller and faster than those using a conventional ROM table.
摘要翻译：用于校正接收到的数字数据字信号中的多个误差的纠错方法和装置根据n个接收数据字块和奇偶校验矩阵H来计算校正子S0，S1，S2和S3。首先将系数sigma1和sigma2从根据第一系数σ1和σ2计算导出的校正子和第二系数K.根据第二系数K计算误差位置值x1，根据值x1计算实际误差位置值X1和X2，并且误差值 Y1和Y2由实际误差位置值X1和X2计算。然后通过应用计算出的误差值Y1和Y2来校正接收到的数据字。误差位置值x1计算器优选地由逻辑门构成，使得装置能够比使用常规ROM表的那些更小和更快。

2. 发明授权

US5227992A Operational method and apparatus over GF(2.sup.m) using a subfield GF(2.sup . 失效
标题翻译： GF（2M）的GF（2M / 2）操作方法和装置
公开(公告)号：US5227992A
公开(公告)日：1993-07-13
申请号：US717506
申请日：1991-06-19
申请人： Man-young Lee , Jae-mun Kim , Hak-song Park , Hyeong-keun An , Heung-yeol Yeom
发明人： Man-young Lee , Jae-mun Kim , Hak-song Park , Hyeong-keun An , Heung-yeol Yeom
IPC分类号： G06F17/10 , G06F7/72 , G11B20/18 , H03M13/03 , H03M13/15
CPC分类号： G06F7/726 , G11B20/1833 , H03M13/033 , H03M13/151 , G06F2207/7209
摘要： An operation method and apparatus over Galois Field GF(2.sup.m) using a subfield GF(2.sup.m/2). The operation apparatus includes a conversion circuit for converting the elements represented by a basis of GF(2.sup.m) into the elements represented by a basis of GF(2.sup.m/2); an operation circuit for performing an operation over GF(2.sup.m/2) with respect to the elements represented by the basis of GF(2.sup.m/2); and a reversion circuit for reverting the operated elements represented by the basis of GF(2.sup.m/2) to the elements represented by the basis of GF(2.sup.m), thereby performing high speed operation and simplifying circuit construction.
摘要翻译：使用子场GF（2m / 2）的Galois Field GF（2m）上的操作方法和装置。该运算装置具有将由GF（2m）的基础表示的元素转换成由GF（2m / 2）的基数表示的元素的转换电路。相对于由GF（2m / 2）的基础表示的元素，对GF（2m / 2）进行运算的运算电路; 以及用于将由GF（2m / 2）的基础表示的操作元件恢复到由GF（2m）的基础表示的元件的逆变电路，由此执行高速操作并简化电路结构。

3. 发明授权

US4942447A Borderless master slice CMOS device 失效
标题翻译：无边界主片CMOS器件
公开(公告)号：US4942447A
公开(公告)日：1990-07-17
申请号：US357038
申请日：1989-05-25
申请人： Hak-song Park , Byoung-jin Choi , Heung-chul Oh
发明人： Hak-song Park , Byoung-jin Choi , Heung-chul Oh
IPC分类号： H01L21/822 , H01L21/301 , H01L21/82 , H01L27/04 , H01L27/118
CPC分类号： H01L27/11807 , H01L2224/05554
摘要： A borderless master slice semiconductor device is disclosed which comprises a plurality of first conduction type well regions arranged in a matrix type on the whole face of a second conduction type wafer; a plurality of second conduction type MOS transistor groups; a plurality of first conduction type diffusion regions arranged alterntely with the said second conduction type MOS transistor groups on the same row; a plurality of first conduction type MOS transistor groups arranged in a row direction facing opposingly with said second conduction type MOS transistor groups; and a plurality of second conduction type diffusion regions arranged alternately with said first conduction type MOS transistor groups on the same row. The device of the present invention thus constituted will bring the result that the master chip can be designed arbitrarily upon to the optimum size correspondingly with customer's order and that the production process can be singularized and the product control can be simplified.
摘要翻译：公开了一种无边界主切片半导体器件，其包括在第二导电型晶片的整个表面上以矩阵型布置的多个第一导电类型阱区域; 多个第二导电型MOS晶体管组; 与所述第二导电型MOS晶体管组交替排列的多个第一导电型扩散区，布置在与所述第二导电型MOS晶体管组相对的行方向上的多个第一导电型MOS晶体管组; 以及与同一行上的所述第一导电型MOS晶体管组交替布置的多个第二导电型扩散区。由此构成的本发明的装置将能够根据客户的订单任意地设计主芯片达到最佳尺寸，并且生产过程可以被奇异化并且可以简化产品控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式