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1. 发明申请

US20070190812A1 SEMICONDUCTOR DEVICE HAVING SUFFICIENT PROCESS MARGIN AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有充分过程的半导体器件及其形成方法
公开(公告)号：US20070190812A1
公开(公告)日：2007-08-16
申请号：US11737675
申请日：2007-04-19
申请人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
发明人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
IPC分类号： H01L21/027
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

2. 发明申请

US20140231925A1 SEMICONDUCTOR DEVICE HAVING SUFFICIENT PROCESS MARGIN AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有充分过程的半导体器件及其形成方法
公开(公告)号：US20140231925A1
公开(公告)日：2014-08-21
申请号：US14264694
申请日：2014-04-29
申请人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
发明人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

3. 发明申请

US20080203590A1 INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITH OVERLAY KEY AND ALIGNMENT KEY AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有覆盖键和对准的集成电路半导体器件及其制造方法
公开(公告)号：US20080203590A1
公开(公告)日：2008-08-28
申请号：US12111651
申请日：2008-04-29
申请人： Chang-Jin KANG , Myeong-Cheol KIM , Man-Hyoung RYOO , Si-Hyeung LEE , Doo-Youl LEE
发明人： Chang-Jin KANG , Myeong-Cheol KIM , Man-Hyoung RYOO , Si-Hyeung LEE , Doo-Youl LEE
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

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