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1. 发明申请

US20080203590A1 INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITH OVERLAY KEY AND ALIGNMENT KEY AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有覆盖键和对准的集成电路半导体器件及其制造方法
公开(公告)号：US20080203590A1
公开(公告)日：2008-08-28
申请号：US12111651
申请日：2008-04-29
申请人： Chang-Jin KANG , Myeong-Cheol KIM , Man-Hyoung RYOO , Si-Hyeung LEE , Doo-Youl LEE
发明人： Chang-Jin KANG , Myeong-Cheol KIM , Man-Hyoung RYOO , Si-Hyeung LEE , Doo-Youl LEE
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

2. 发明申请

US20090008701A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090008701A1
公开(公告)日：2009-01-08
申请号：US11555126
申请日：2006-10-31
申请人： Dong-Hyun KIM , Gyung-Jin MIN , Chang-Jin KANG , Seung-Pil CHUNG
发明人： Dong-Hyun KIM , Gyung-Jin MIN , Chang-Jin KANG , Seung-Pil CHUNG
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/517
摘要： A nonvolatile memory device includes a semiconductor substrate, a charge trap layer formed on the semiconductor substrate, a blocking layer formed on the charge trap layer, and a gate electrode formed on the blocking layer. Sides of blocking layer extend laterally beyond sides of the charge trap layer and lateral sides of the gate electrode.
摘要翻译：非易失性存储器件包括半导体衬底，形成在半导体衬底上的电荷阱层，形成在电荷陷阱层上的阻挡层和形成在阻挡层上的栅电极。阻挡层的侧面横向延伸超过电荷陷阱层的侧面和栅电极的侧边。

3. 发明申请

US20090263970A1 METHOD OF FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE USING SIGE LAYER AS SACRIFICIAL LAYER, AND METHOD OF FORMING SELF-ALIGNED CONTACTS USING THE SAME 有权
标题翻译：使用信号层作为绝对层形成半导体器件的精细图案的方法和使用其形成自对准接触的方法
公开(公告)号：US20090263970A1
公开(公告)日：2009-10-22
申请号：US12496108
申请日：2009-07-01
申请人： Keun-Hee BAI , Kyeong-Koo CHI , Chang-Jin KANG , Cheol-Kyu LEE
发明人： Keun-Hee BAI , Kyeong-Koo CHI , Chang-Jin KANG , Cheol-Kyu LEE
IPC分类号： H01L21/768
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

4. 发明申请

US20080057733A1 METHOD OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20080057733A1
公开(公告)日：2008-03-06
申请号：US11847223
申请日：2007-08-29
申请人： Seung-Pil CHUNG , Dong-Chan KIM , Chang-Jin KANG , Heung-Sik PARK
发明人： Seung-Pil CHUNG , Dong-Chan KIM , Chang-Jin KANG , Heung-Sik PARK
IPC分类号： H01L21/31
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086
摘要： Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.
摘要翻译：公开了制造半导体集成电路器件的方法。制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。根据本发明的方法比常规方法更简单和便宜。

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